초록 ▼

Generally, Reed-Solomon encoding process in the conventional communication system is executed by a Reed-Solomon encoder having different code rates for different data transmission rates. The present invention does not use a Reed-Solomon encoder having different coding rates, but instead uses a Reed-

Generally, Reed-Solomon encoding process in the conventional communication system is executed by a Reed-Solomon encoder having different code rates for different data transmission rates. The present invention does not use a Reed-Solomon encoder having different coding rates, but instead uses a Reed-Solomon encoder having the same code rate regardless of data transmission rate. Accordingly, the present invention has the following effects. The present invention maintains same communication quality regarding data services having each different data transmission rate, and can use a single Reed-Solomon encoder.

대표청구항 ▼

[ What is claimed is:] [1.] A channel encoding apparatus using a concatenated encoder, comprising:a data block former for forming subdata blocks with constant size and grouped according to a plurality of different data transmission rates;a serial/parallel converter for converting the subdata blocks

[ What is claimed is:] [1.] A channel encoding apparatus using a concatenated encoder, comprising:a data block former for forming subdata blocks with constant size and grouped according to a plurality of different data transmission rates;a serial/parallel converter for converting the subdata blocks formed by the data block former into several message symbols;a Reed-Solomon encoder for outputting the message symbols converted by the serial/parallel converter, and computing several parity check symbols according to the message symbols to generate Reed-Solomon code symbols;a parallel/serial converter for converting the Reed-Solomon code symbols generated by the Reed-Solomon encoder into serial data bits;a zero tail adder for adding eight zero tail bits to the serial data bits from the parallel/serial converter; anda convolutional encoder for convolutionally encoding the output data bits from the zero tail adder.