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Pre-semiconductor process implant and post-process film separation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/425
출원번호 US-0371589 (1999-08-10)
발명자 / 주소
  • Henley Francois J.
  • Cheung Nathan W.
출원인 / 주소
  • Silicon Genesis Corporation
대리인 / 주소
    Townsend and Townsend and Crew LLP
인용정보 피인용 횟수 : 135  인용 특허 : 16

초록

A process for forming a novel substrate material. The process includes providing a substrate, e.g., silicon wafer. The substrate has a stressed layer at a selected depth underneath a surface of the substrate. The stressed layer is at the selected depth to define a substrate material to be removed ab

대표청구항

[ What is claimed is:] [1.] A process for forming electronic devices, the process comprising steps:providing a substrate, the substrate comprising a stressed layer at a selected depth underneath a surface of the substrate, the stressed layer being at the selected depth to define a substrate material

이 특허에 인용된 특허 (16)

  1. Matsushita Takeshi,JPX ; Morita Etsuo,JPX ; Nakajima Tsuneo,JPX ; Hasegawa Hiroyuki,JPX ; Shingyouji Takayuki,JPX, A SOI substrate fabricating method.
  2. Frank Walter (Burgkirchen DEX) Pemwieser Albert (Ach ATX) Spatzier Gerhard (Eggelsberg ATX), Apparatus and method of automatically separating stacked wafers.
  3. Yonehara Takao,JPX, Method for bonding semiconductor substrates.
  4. Henley Francois J. ; Cheung Nathan W., Method for controlled cleaving process.
  5. Lee Sahng Kyoo,KRX ; Park Sang Kyun,KRX, Method for fabricating semiconductor wafers.
  6. Wijaranakula Witawat (Vancouver WA), Method for manufacturing a calibration wafer having a microdefect-free layer of a precisely predetermined depth.
  7. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Method for producing semiconductor substrate.
  8. Hayashi Yutaka (Tsukuba JPX) Takahashi Kunihiro (Tokyo JPX) Takasu Hiroaki (Tokyo JPX) Kojima Yoshikazu (Tokyo JPX) Niwa Hitoshi (Tokyo JPX) Matsuyama Nobuyoshi (Tokyo JPX) Yoshino Yomoyuki (Tokyo JP, Method of making semiconductor device with multiple transparent layers.
  9. Bozler Carl O. (Sudbury MA) Fan John C. C. (Chestnut Hill MA) McClelland Robert W. (Weymouth MA), Method of producing sheets of crystalline material.
  10. Wilkes Donald F. (Albuquerque NM), Process for cleaving crystalline materials.
  11. Harada Keizo (Itami JPX) Maeda Takao (Itami JPX) Takikawa Takatoshi (Itami JPX) Ban Shunsuke (Itami JPX) Yamanaka Shosaku (Itami JPX), Process for manufacturing a semiconductor substrate comprising laminated copper, silicon oxide and silicon nitride layer.
  12. Hanson David R. ; Huston ; III Hance H. ; Srikrishnan Kris V., Process for restoring rejected wafers in line for reuse as new.
  13. Kramler, Josef; Kuhn-Kuhnenfeld, Franz; Gerber, Hans-Adolf, Process for the manufacture of semiconductor wafers with a rear side having a gettering action.
  14. Bruel Michel,FRX, Process for the manufacture of thin films of semiconductor material.
  15. Srikrishnan Kris V., Smart-cut process for the production of thin semiconductor material films.
  16. Bruel Michel,FRX, Structure having cavities and process for producing such a structure.

이 특허를 인용한 특허 (135)

  1. Adibi, Babak; Murrer, Edward S., Application specific implant system and method for use in solar cell fabrications.
  2. Nunan, Peter; Walther, Steven R.; Erokhin, Yuri; Sullivan, Paul J., Cleave initiation using varying ion implant dose.
  3. Francois J. Henley ; Michael A. Brayan ; William G. En, Cleaving process to fabricate multilayered substrates using low implantation doses.
  4. Henley,Francois J.; Bryan,Michael A.; En,William G., Cleaving process to fabricate multilayered substrates using low implantation doses.
  5. Currie,Matthew T., Control of strain in device layers by prevention of relaxation.
  6. Currie,Matthew T., Control of strain in device layers by selective relaxation.
  7. Francois J. Henley ; Nathan Cheung, Controlled cleavage process and device for patterned films.
  8. Henley, Francois J.; Cheung, Nathan, Controlled cleavage process and device for patterned films.
  9. Francois J. Henley ; Nathan W. Cheung, Controlled cleavage process and resulting device using beta annealing.
  10. Henley, Francois J.; Cheung, Nathan, Controlled cleavage process using pressurized fluid.
  11. Henley, Francois J.; Cheung, Nathan W., Controlled cleaving process.
  12. Henley,Francois J.; Cheung,Nathan W., Controlled cleaving process.
  13. Henley,Francois J.; Cheung,Nathan W., Controlled cleaving process.
  14. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  15. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  16. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  17. Henley,Francois J.; Cheung,Nathan W., Controlled process and resulting device.
  18. Fitzgerald, Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
  19. Fitzgerald,Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
  20. Fitzgerald,Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
  21. Blake, Julian G.; Murphy, Paul J., Cooled cleaving implant.
  22. Hiliali, Mohamed M.; Herner, S. Brad, Creation and translation of low-relief texture for a photovoltaic cell.
  23. Li, Zhiyong; Tanner, David; Prabhu, Gopalakrishna; Hilali, Mohamed H., Creation of low-relief texture for a photovoltaic cell.
  24. Lochtefeld, Anthony J.; Langdo, Thomas A.; Westhoff, Richard, Elevated source and drain elements for strained-channel heterojuntion field-effect transistors.
  25. Wu,Kenneth C.; Fitzgerald,Eugene A.; Taraschi,Gianni; Borenstein,Jeffrey T., Etch stop layer system.
  26. Letertre, Fabrice; Ghyselen, Bruno; Rayssac, Olivier, Fabrication of substrates with a useful layer of monocrystalline semiconductor material.
  27. Lagahe,Chrystelle; Aspar,Bernard; Beaumont,Aur?lie, Formation of a semiconductor substrate that may be dismantled and obtaining a semiconductor element.
  28. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  29. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  30. Prabhakar, Vinay; Adibi, Babak, Grid for plasma ion implant.
  31. Prabhakar, Vinay; Adibi, Babak, Grid for plasma ion implant.
  32. Fitzgerald, Eugene A., Heterointegration of materials using deposition and bonding.
  33. Fitzgerald, Eugene A., Heterointegration of materials using deposition and bonding.
  34. Fitzgerald, Eugene A., Heterointegration of materials using deposition and bonding.
  35. Currie, Matthew T., Hybrid fin field-effect transistor structures and related methods.
  36. Anella, Steven M.; Weaver, William, Implanting a solar cell substrate using a mask.
  37. Adibi, Babak; Chun, Moon, Ion implant system having grid assembly.
  38. Adibi, Babak; Chun, Moon, Ion implant system having grid assembly.
  39. Adibi, Babak; Chun, Moon, Ion implant system having grid assembly.
  40. Henley, Francois J., Layer transfer of films utilizing controlled propagation.
  41. Henley, Francois J., Layer transfer of films utilizing controlled shear region.
  42. Fitzgerald, Eugene A., Low threading dislocation density relaxed mismatched epilayers without high temperature growth.
  43. Faris,Sadeg M., MEMS and method of manufacturing MEMS.
  44. Francois J. Henley ; Nathan W. Cheung, Method and device for controlled cleaving process.
  45. Henley, Francois J.; Cheung, Nathan W., Method and device for controlled cleaving process.
  46. Henley,Francois J.; Cheung,Nathan, Method and device for controlled cleaving process.
  47. Henley, Francois J., Method and structure for fabricating solar cells using a thick layer transfer process.
  48. Henley, Francois J.; Lamm, Albert; Adibi, Babak, Method and structure for thick layer transfer using a linear accelerator.
  49. Henley,Francois J., Method for fabricating semiconductor devices using strained silicon bearing material.
  50. Henley,Francois J., Method for fabricating semiconductor devices using strained silicon bearing material.
  51. Adibi, Babak; Chun, Moon, Method for ion implant using grid assembly.
  52. Henley, Francois J., Method of cleaving a thin sapphire layer from a bulk material by implanting a plurality of particles and performing a controlled cleaving process.
  53. Graff, John; Bateman, Nicholas; Olson, Joseph; Riordon, Benjamin, Method of creating two dimensional doping patterns in solar cells.
  54. Tong,Qin Yi; Fountain, Jr.,Gaius Gillman, Method of detachable direct bonding at low temperatures.
  55. Fitzgerald, Eugene A.; Gerrish, Nicole, Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs.
  56. Fitzgerald, Eugene A.; Gerrish, Nicole, Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS.
  57. Cheng,Zhiyuan; Fitzgerald,Eugene A.; Antoniadis,Dimitri A., Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers.
  58. Faris,Sadeg M., Method of fabricating multi layer devices on buried oxide layer substrates.
  59. Neng-Hui Yang TW; Ming-Sheng Yang TW; Chien-Mei Wang TW, Method of removing silicon carbide.
  60. Sivaram, Srinivasan; Agarwal, Aditya; Herner, S. Brad; Petti, Christopher J., Method to form a photovoltaic cell comprising a thin lamina.
  61. Sivaram, Srinivasan; Agarwal, Aditya; Herner, S. Brad; Petti, Christopher J., Method to form a photovoltaic cell comprising a thin lamina.
  62. Sivaram, Srinivasan; Agarwal, Aditya; Herner, S. Brad; Petti, Christopher J., Method to form a photovoltaic cell comprising a thin lamina.
  63. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.
  64. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.
  65. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming III-V semiconductor device structures.
  66. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain.
  67. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes.
  68. Fitzgerald, Eugene A., Methods of fabricating contact regions for FET incorporating SiGe.
  69. Vineis,Christopher; Yang,Vicky; Currie,Matthew; Westhoff,Richard; Leitz,Christopher, Methods of fabricating semiconductor heterostructures.
  70. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.
  71. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.
  72. Currie,Matthew T., Methods of forming hybrid fin field-effect transistor structures.
  73. Currie,Matthew T.; Hammond,Richard, Methods of forming reacted conductive gate electrodes.
  74. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods of forming strained-semiconductor-on-insulator device structures.
  75. Lochtefeld,Anthony J.; Langdo,Thomas A.; Hammond,Richard; Currie,Matthew T.; Braithwaite,Glyn; Fitzgerald,Eugene A., Methods of forming strained-semiconductor-on-insulator finFET device structures.
  76. Dickerson, Gary E.; Blake, Julian G., Modulating implantation for improved workpiece splitting.
  77. Fitzgerald, Eugene A., Monolithically integrated light emitting devices.
  78. Fitzgerald, Eugene A., Monolithically integrated photodetectors.
  79. Fitzgerald, Eugene A., Monolithically integrated semiconductor materials and devices.
  80. Fitzgerald, Eugene A., Monolithically integrated silicon and III-V electronics.
  81. Malik, Igor J.; Kang, Sien G.; Fuerfanger, Martin; Kirk, Harry; Flat, Ariel; Current, Michael Ira; Ong, Philip James, Non-contact etch annealing of strained layers.
  82. Bryan, Michael A.; Kai, James K., Nozzle for cleaving substrates.
  83. Bryan, Michael A., Particle distribution method and resulting structure for a layer transfer process.
  84. Sullivan, Paul; Nunan, Peter; Walther, Steven R., Patterned assembly for manufacturing a solar cell and a method thereof.
  85. Sullivan, Paul; Nunan, Peter; Walther, Steven R., Patterned assembly for manufacturing a solar cell and a method thereof.
  86. Hilali, Mohamed M.; Petti, Christopher J., Photovoltaic cell comprising a thin lamina having low base resistivity and method of making.
  87. Adibi, Babak; Chun, Moon, Plasma grid implant system for use in solar cell fabrications.
  88. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.
  89. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.
  90. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.
  91. Braithwaite, Glyn; Hammond, Richard; Currie, Matthew, RF circuits including transistors having strained material layers.
  92. Braithwaite, Glyn; Hammond, Richard; Currie, Matthew, RF circuits including transistors having strained material layers.
  93. Henley, Francois J.; Brailove, Adam, Race track configuration and method for wafering silicon solar substrates.
  94. Currie, Matthew T.; Hammond, Richard, Reacted conductive gate electrodes.
  95. Vineis, Christopher J.; Westhoff, Richard; Bulsara, Mayank, Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy.
  96. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.
  97. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.
  98. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
  99. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
  100. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
  101. Wells, David H.; Manning, H. Montgomery, Reverse construction integrated circuit.
  102. Wells, David H.; Manning, H. Montgomery, Reverse construction memory cell.
  103. Wells, David H.; Manning, H. Montgomery, Reverse construction memory cell.
  104. Faris,Sadeg M., Selectively bonded thin film layer and substrate layer for processing of useful devices.
  105. Cheng, Zhiyuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A., Semiconductor device structure.
  106. Vineis,Christopher; Yang,Vicky; Currie,Matthew; Westhoff,Richard; Leitz,Christopher, Semiconductor heterostructures and related methods.
  107. Westhoff,Richard; Yang,Vicky; Currie,Matthew; Vineis,Christopher; Leitz,Christopher, Semiconductor heterostructures having reduced dislocation pile-ups.
  108. Westhoff, Richard; Yang, Vicky K.; Currie, Matthew T.; Vineis, Christopher; Leitz, Christopher, Semiconductor heterostructures having reduced dislocation pile-ups and related methods.
  109. Mori, Michael J.; Fitzgerald, Eugene A., Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission.
  110. Sinha, Nishant; Sandhu, Gurtej S.; Smythe, John, Semiconductor material manufacture.
  111. Currie, Matthew T.; Lochtefeld, Anthony J.; Hammond, Richard; Fitzgerald, Eugene A., Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.
  112. Currie, Matthew T.; Lochtefeld, Anthony J.; Hammond, Richard; Fitzgerald, Eugene A., Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.
  113. Currie, Matthew; Lochtefeld, Anthony; Hammond, Richard; Fitzgerald, Eugene, Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.
  114. Westhoff,Richard; Vineis,Christopher J.; Currie,Matthew T.; Yang,Vicky T.; Leitz,Christopher W., Semiconductor structures with structural homogeneity.
  115. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Semiconductor substrate structure.
  116. Currie,Matthew T.; Lochtefeld,Anthony J., Shallow trench isolation process.
  117. Henley, Francois J.; Cheung, Nathan W., Silicon-on-silicon hybrid wafer assembly.
  118. Adibi, Babak; Murrer, Edward S., Solar cell fabrication with faceting and ion implantation.
  119. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained germanium-on-insulator device structures.
  120. Fitzgerald,Eugene A.; Pitera,Arthur J., Strained gettering layers for semiconductor processes.
  121. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  122. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  123. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures with elevated source/drain regions.
  124. Langdo,Thomas A.; Currie,Matthew T.; Braithwaite,Glyn; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator finFET device structures.
  125. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  126. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  127. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  128. Pederson, Terry; Hieslmair, Henry; Chun, Moon; Prabhakar, Vinay; Adibi, Babak; Bluck, Terry, Substrate processing system and method.
  129. Pederson, Terry; Hieslmair, Henry; Chun, Moon; Prabhakar, Vinay; Adibi, Babak; Bluck, Terry, Substrate processing system and method.
  130. Brailove, Adam; Liu, Zuqin; Henley, Francois J.; Lamm, Albert J., Techniques for forming thin films by implantation with reduced channeling.
  131. Anella, Steven M., Techniques for manufacturing solar cells.
  132. Bateman, Nicholas; Gupta, Atul; Sullivan, Paul; Murphy, Paul, Use of chained implants in solar cells.
  133. Bateman, Nicholas; Gupta, Atul; Hatem, Christopher; Ramappa, Deepak, Use of dopants with different diffusivities for solar cell manufacture.
  134. Ricci, Justin M., Using multiple masks to form independent features on a workpiece.
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