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Method to create a controllable and reproducible dual copper damascene structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/476
출원번호 US-0390782 (1999-09-07)
발명자 / 주소
  • Ho Paul Kwok Keung,SGX
  • Zhou Mei Sheng,SGX
  • Gupta Subhash,SGX
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd., SGX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 73  인용 특허 : 6

초록

A new method is provided to construct a copper dual damascene structure. A layer of IMD is deposited over the surface of a substrate. A cap layer is deposited over this layer of IMD, the dual damascene structure is then patterned through the cap layer and into the layer of IMD. A barrier layer is bl

대표청구항

[ What is claimed is:] [1.] A method of creating a copper dual damascene structure on the surface of a semiconductor substrate, comprising the steps of:providing a semiconductor substrate the surface of said substrate to contain metal contact points;forming an opening for a dual damascene structure

이 특허에 인용된 특허 (6)

  1. Avanzino Steven ; Gupta Subhash ; Klein Rich ; Luning Scott D. ; Lin Ming-Ren, Dual damascene with a sacrificial via fill.
  2. Ting Chiu H. (Saratoga CA) Pai Pei-Lin (Cupertino CA), Fully planar metalization process.
  3. Koh Chao-Ming (Hsinchu TWX) Chien Rong-Wu (Chyai TWX), Method for fabricating stacked capacitors in a DRAM cell.
  4. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  5. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  6. Venkatraman Ramnath ; Mendonca John ; Hamilton Gregory N. ; Wetzel Jeffrey T. ; Poon Tze W. ; Garcia Sam S., Semiconductor device with a copper barrier layer and formation thereof.

이 특허를 인용한 특허 (73)

  1. Cohen, Uri, Advanced seed layers for interconnects.
  2. Cohen,Uri, Advanced seed layery for metallic interconnects.
  3. Cohen, Uri, Apparatus for depositing seed layers.
  4. Cohen, Uri, Apparatus for making interconnect seed layers and products.
  5. Chen, Ling; Marcadal, Christophe, Barrier layer structure for copper metallization and method of forming the structure.
  6. Woo, Christy Mei-Chu; Marathe, Amit P., Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP.
  7. Akinmade-Yusuff, Hakeem B. S.; Choi, Samuel Sung Shik; Engbrecht, Edward R.; Fitzsimmons, John A., Bilayer trench first hardmask structure and process for reduced defectivity.
  8. Cohen, Uri, Combined conformal/non-conformal seed layers for metallic interconnects.
  9. Chen, Ling; Ganguli, Seshadri; Marcadal, Christophe; Cao, Wei; Mosely, Roderick C.; Chang, Mei, Copper interconnect barrier layer structure and formation method.
  10. Chen, Shyng-Tsong; Dalton, Timothy J.; Davis, Kenneth M.; Hu, Chao-Kun; Jamin, Fen F.; Kaldor, Steffen K.; Krishnan, Mahadevaiyer; Kumar, Kaushik; Lofaro, Michael F.; Malhotra, Sandra G.; Narayan, Ch, Copper recess process with application to selective capping and electroless plating.
  11. Chen,Shyng Tsong; Dalton,Timothy J.; Davis,Kenneth M.; Hu,Chao Kun; Jamin,Fen F.; Kaldor,Steffen K.; Krishnan,Mahadevaiyer; Kumar,Kaushik; Lofaro,Michael F.; Malhotra,Sandra G.; Narayan,Chandrasekhar, Copper recess process with application to selective capping and electroless plating.
  12. Turner, Michael D.; Chatterjee, Ritwik; Filipiak, Stanley M., Dual plasma treatment barrier film to reduce low-k damage.
  13. Chen, Ling; Chung, Hua; Chin, Barry L.; Zhang, Hong, Enhanced copper growth with ultrathin barrier layer for high performance interconnects.
  14. Chen, Ling; Chung, Hua; Chin, Barry L.; Zhang, Hong, Enhanced copper growth with ultrathin barrier layer for high performance interconnects.
  15. Lu, Chia-Lin; Chen, Chun-Lung; Liao, Kun-Yuan; Liao, Jiunn-Hsiung; Huang, Wei-Hao; Cheng, Kai-Teng, Fabrication method and structure of semiconductor device with contact and plug.
  16. Chiras, Stefanie Ruth; Lane, Michael Wayne; Malhotra, Sandra Guy; Mc Feely, Fenton Reed; Rosenberg, Robert; Sambucetti, Carlos Juan; Vereecken, Philippe Mark, Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures.
  17. Lin, Chun Chieh; Su, Hung-Wen; Tsai, Minghsing; Jang, Syun-Ming, Gap filling method for dual damascene process.
  18. Weng, Chun-Jen; Chen, Juan-Yi; Pan, Hong-Tsz; Lee, Cedric; Wu, Der-Yuan; Lin, Jackson; Yen, Yeong-Song; Lin, Lawrence; Tseng, Ying-Chung, Gap-filling process.
  19. Li, Sam Fong Yau; Ng, Hou Tee, Highly selective and complete interconnect metal line and via/contact hole filling by electroless plating.
  20. Cohen, Uri, Metallic interconnects products.
  21. Daubenspeck, Timothy H.; Landers, William F.; Zupanski-Nielsen, Donna S., Method for fabricating last level copper-to-C4 connection with interfacial cap structure.
  22. Jong Chen TW; Tze-Liang Lee TW; Fan-Keng Yang TW, Method for forming a passivation layer on copper conductive elements.
  23. Chen, Chien-Hui; Yang, Ming-Kun; Liu, Tsang-Yu; Ho, Yen-Shih, Method for forming chip package.
  24. Shim, Cheon Man, Method for forming metal line of semiconductor device.
  25. Ebrahim Andideh ; Alan M. Myers, Method for making a semiconductor device that has a dual damascene interconnect.
  26. Hsu, Heng-Ming; Chung, Jau-Yuann; Ho, Yen-Shih; Chen, Chun-Hon; Peng, Kuo-Reay; Yeh, Ta-Hsun; Thei, Kong-Beng; Ma, Ssu-Pin, Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process.
  27. Sung Gyu Pyo KR, Method of forming a metal wiring in a semiconductor device.
  28. Park,Sang Kyun, Method of forming copper wiring in semiconductor device.
  29. Lim, Victor Seng-Keong; Chooi, Simon; Cha, Randall, Method to fabricate dish-free copper interconnects.
  30. Victor Seng Keong Lim SG; Feng Chen SG; Wang Ling Goh SG, Method to prevent CU dishing during damascene formation.
  31. Simon Chooi SG; Mei Sheng Zhou SG; Tak Yan Tse SG, Method to remove excess metal in the formation of damascene and dual interconnects.
  32. Cohen, Uri, Methods for making multiple seed layers for metallic interconnects.
  33. Tang,Sanh D.; Gugel,Troy; Lee,John; Fishburn,Fred, Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces.
  34. Cohen,Uri, Multiple seed layers for interconnects.
  35. Cohen, Uri, Multiple seed layers for metallic interconnects.
  36. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  37. Chad R. Binkerd ; Jose L. Cruz ; Timothy C. Krywanczyk ; Brian D. Pfeifer ; Rosemary A. Previti-Kelly ; Patricia Schink ; Amye L. Wells, Prevention of slurry build-up within wafer topography during polishing.
  38. Subhash Gupta SG; Mei-Sheng Zhou SG; Simon Chooi SG; Sangki Hong SG, Reversed damascene process for multiple level metal interconnects.
  39. Cohen, Uri, Seed layers for metallic interconnects.
  40. Cohen,Uri, Seed layers for metallic interconnects.
  41. Cohen, Uri, Seed layers for metallic interconnects and products.
  42. Chung, Dean S.; Horak, David V.; Walton, Erick G., Selective deposition of a conductive material.
  43. Morgan, Paul A.; Sinha, Nishant, Selective metal deposition over dielectric layers.
  44. Morgan, Paul A; Sinha, Nishant, Selective metal deposition over dielectric layers.
  45. Morgan, Paul A; Sinha, Nishant, Selective metal deposition over dielectric layers.
  46. Kawamura, Kazuo; Akiyama, Shinichi; Takesako, Satoshi, Semiconductor device and method of manufacturing the same.
  47. Ngo Minh Van ; Wang Fei, Semiconductor device comprising copper interconnects with reduced in-line diffusion.
  48. Lin, Chun-Chieh; Su, Hung-Wen; Tsai, Ming-Hsing; Jang, Syun-Ming, Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components.
  49. Lin, Chun-Chieh; Su, Hung-Wen; Tsai, Ming-Hsing; Jang, Syun-Ming, Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components.
  50. Hendler, Larry; Zehavi, Sharone; Dulkin, Tanya; Zehavi, Raanan Y., Surface characteristics of graphite and graphite foils.
  51. Singh, Bhanwar; Templeton, Michael K.; Rangarajan, Bharath; Subramanian, Ramkumar, Systems and methods to determine seed layer thickness of trench sidewalls.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  59. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  60. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  61. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  62. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  63. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  64. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  65. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  66. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  67. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  68. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  69. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  70. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  71. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  72. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  73. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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