초록 ▼

A packaged integrated circuit device with a multi-level lead frame has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower lead frame and an upper lead frame, one of the lead frames being subdivided into a plurality of portions, each subdivided portion with a

A packaged integrated circuit device with a multi-level lead frame has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower lead frame and an upper lead frame, one of the lead frames being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

대표청구항 ▼

[ What is claimed is:] [1.] A package integrated circuit device assembly comprising:an integrated circuit chip having at least one integrated circuit therein, said integrated circuit chip having a first active surface having, in turn, at least one contact pad arranged thereon and having a second sur

[ What is claimed is:] [1.] A package integrated circuit device assembly comprising:an integrated circuit chip having at least one integrated circuit therein, said integrated circuit chip having a first active surface having, in turn, at least one contact pad arranged thereon and having a second surface;an upper conductive planar lead frame member having an upper surface mounting said second surface of said integrated circuit chip thereto using an electrically insulative adhesive, and having a lower surface, said upper conductive planar lead frame member subdivided into a plurality of portions, at least one portion of said plurality of portions having an exposed tab connected to said at least one integrated circuit of said integrated circuit chip;a lower conductive planar lead frame member having an upper surface mounting said upper conductive planar lead frame member using a thin intervening layer of dielectric material whereby capacitance results, said lower lead frame conductive planar lead frame member cooperating with said upper conductive planar lead frame member;at least one lead of a plurality of leads connecting said at least one contact pad to at least one lead finger; andat least one other lead of said plurality of leads connected to at least one tab of said upper conductive planar lead frame member.