초록 ▼

Power consumption in medical devices is reduced through the use and operation of multiple digital signal processing systems. Each processor of the multiple systems performs at least one particular function in a predetermined time period. The multiple digital signal processors of such systems can be

Power consumption in medical devices is reduced through the use and operation of multiple digital signal processing systems. Each processor of the multiple systems performs at least one particular function in a predetermined time period. The multiple digital signal processors of such systems can be operated at lower clock frequencies relative to those that would be required by one of such processors to complete the multiple functions within the predetermined time period. With reduced clock frequency, power consumption is reduced. Further, with reduced clock speed, supply voltages applied to such digital signal processors may also be reduced.

대표청구항 ▼

[ I claim:] [1.] A medical device adapted to be implanted in a living body for delivering a therapy to a patient's body or monitoring a physiologic condition of a patient comprising:an electrical stimulation therapy delivery circuits; and a physiological condition monitoring circuit;a battery to pro

[ I claim:] [1.] A medical device adapted to be implanted in a living body for delivering a therapy to a patient's body or monitoring a physiologic condition of a patient comprising:an electrical stimulation therapy delivery circuits; and a physiological condition monitoring circuit;a battery to provide battery energy; andan operating system powered by the battery energy providing control and timing functions associated with the delivery of the therapy to the patient's body or monitoring a physiologic condition of the patient further comprising:a system clock circuit powered by the battery energy and having a first output clock signal at a first clock frequency and a second output clock signal at a second clock frequency;means for timing a predetermined time period;a first analog signal input;a second analog signal input; anda first digital signal processing system receiving the first analog input, the first digital signal processing system including first digital signal processor operating at the first clock frequency on the first analog input to convert the analog input into a first digital data signal and to perform at least a first detection function during the predetermined time period; anda second digital signal processing system receiving the second analog input, the second digital signal processing system including a second digital signal processor operating at the second clock frequency on the second analog input to convert the analog input into a second digital data signal and to perform at least a second detection function during the predetermined time period,wherein the first and second clock frequencies reduce the power consumed by the first and second digital signal processors in performance of the first and second detection functions to a level that is less than the power that would be consumed if only one of the first and second digital signal processors were to perform both of the first and second detection functions within the predetermined time period.