초록 ▼

A digital signal processor which supports an instruction set including both 16-bit instructions and 32-bit instructions, so that particular portions of a program requiring only 16-bit instructions may be encoded in a 16-bit mode, thus reducing the program memory needed to store these portions. The d

A digital signal processor which supports an instruction set including both 16-bit instructions and 32-bit instructions, so that particular portions of a program requiring only 16-bit instructions may be encoded in a 16-bit mode, thus reducing the program memory needed to store these portions. The digital signal processor switches between the 16- and 32-bit modes only in response to flow control instructions such as JUMP, CALL or RETURN instructions. JUMP and CALL instructions are coded to indicate the processor mode applicable to the instructions to which the JUMP or CALL instruction goes to, so that the processor may change modes as needed when executing the JUMP or CALL instruction. When a CALL is executed the current processor mode is stored on the processor's stack, so that in response to a RETURN instruction the processor can return to this mode by retrieving the stored mode from the stack.

대표청구항 ▼

[ What is claimed is:] [1.] A digital signal processor, comprising:a program memory storing instructions comprising a program for said digital signal processor, said instructions including short instructions having a first number of digital signals and long instructions having a second number of dig

[ What is claimed is:] [1.] A digital signal processor, comprising:a program memory storing instructions comprising a program for said digital signal processor, said instructions including short instructions having a first number of digital signals and long instructions having a second number of digital signals greater than said first number of digital signals of said short instructions, wherein said program memory comprises a first section and a second section, said long instructions being stored in said first section and said second section, each said short instruction being stored in a single entry of said first or second sections;a program control unit retrieving instructions from said program memory, and responding to said instructions by generating command signals controlling operations of other units of said digital signal processor, said program control unit having a first mode in which said program control unit retrieves and responds to said short instructions and retrieves and responds to long instruction from either said first or said second sections of said program memory, and a second mode in which said program control unit retrieves and responds only to long instructions from both said first and said second sections of said program memory;a register file storing digital data;an address generator unit connected to a digital data bus, said register file and to said program control unit and responding to command signals to retrieve and store data from and to a digital data memory to and from said register file via said digital data bus; andat least one logic unit connected to said program control unit and to said register file and responding to command signals to perform digital data processing upon data in said register file.