초록 ▼

A semiconductor manufacturing process with improved gap fill capabilities is provided by a three step process of FSG deposition/etchback/FSG deposition. A first layer of FSG is partially deposited over a metal layer. An argon sputter etchback step is then carried out to etch out excess deposition ma

A semiconductor manufacturing process with improved gap fill capabilities is provided by a three step process of FSG deposition/etchback/FSG deposition. A first layer of FSG is partially deposited over a metal layer. An argon sputter etchback step is then carried out to etch out excess deposition material. Finally, a second layer of FSG is deposited to complete the gap fill process.

대표청구항 ▼

[ What is claimed is:] [1.] A process for depositing an intermetal dielectric film on a substrate having a patterned metal layer formed over an upper surface of said substrate, said patterned metal layer including a first and second parallel lines having inner edges that define a gap of 0.45 microns

[ What is claimed is:] [1.] A process for depositing an intermetal dielectric film on a substrate having a patterned metal layer formed over an upper surface of said substrate, said patterned metal layer including a first and second parallel lines having inner edges that define a gap of 0.45 microns or less in width between said first and second parallel lines, said process comprising:depositing a first fluorine-doped silicon oxide layer of said intermetal dielectric film over the first and second parallel lines, said first fluorine-doped silicon oxide layer having a bottom portion deposited within said gap, upper portions deposited over said first and second metal lines, and sidewall portions extending from said bottom portion to upper portions, said sidewall portion having corner regions at least partially overhanging said bottom portion;etching a portion of said first fluorine-doped silicon oxide layer by sputtering said first fluorine-doped silicon oxide layer with an inert gas to remove said overhanging corner regions of the sidewall portion of said first fluorine-doped silicon oxide layer; anddepositing a second fluorine-doped silicon oxide layer over said first fluorine-doped silicon oxide layer to fill said gap between said first and second parallel lines.