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Mapping heterogeneous logic elements in a programmable logic device

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-017/50   
미국특허분류(USC) 716/018 ; 716/016
출원번호 US-0169213 (1998-10-09)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Beyer Weaver & Thomas, LLP
인용정보 피인용 횟수 : 79  인용 특허 : 4
초록

A method and mechanism for mapping heterogeneous logic elements in a portion of electronic design compilation for a programmable integrated circuit is disclosed. Specifically, the invention provides a method to perform the technology mapping of heterogeneous logic elements in a programmable logic device such as selectively choosing the best combination of product term logic elements and look up table logic elements.

대표
청구항
▼

[What is claimed is:] [1.](a) forming a first logical region using the first type logic element;(b) forming a second logical region using the second type logic element, wherein the first logical region and the second logical region perform logically equivalent sub-functions of the electronic design;(c) comparing the first and the second logical regions;(d) choosing either the first logical region or the second logical region based upon the comparing (c);(e) adding the chosen logical region from operation (d) to a final mapping list; and(f) repeating oper...

이 특허에 인용된 특허 (4)

  1. Tse John ; Lee Fung Fung ; Mendel David Wolk. Fitting for incremental compilation of electronic designs. USP2000086102964.
  2. Bertolet Allan Robert ; Clinton Kim P. N. ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Reny Timothy Shawn ; Zittritsch Terrance John. Method and system for layout and schematic generation for heterogeneous arrays. USP1998035734582.
  3. Harrison David A. (Cupertino CA) Silver Joshua M. (Sunnyvale CA) Soe Soren T. (San Jose CA). Method for programming complex PLD having more than one function block type. USP1997065636368.
  4. Damarla T. Raju ; Su Wei. Methods and computer programs for minimizing logic circuit design using identity cells. USP1999105974242.

이 특허를 인용한 특허 피인용횟수: 79

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