초록 ▼

A CMOS charge-integration mode photo-detector built on an n-type substrate is disclosed in this invention. This photo-detector includes a p+n photodiode with the n-type substrate constituting an n-region and a p+ diffusion region disposed near a top surface of the n-type substrate, the p+ diffusion

A CMOS charge-integration mode photo-detector built on an n-type substrate is disclosed in this invention. This photo-detector includes a p+n photodiode with the n-type substrate constituting an n-region and a p+ diffusion region disposed near a top surface of the n-type substrate, the p+ diffusion region constituting a charge integration node. The photodetector further includes a gate-biased charge storable n-type MOS transistor functioning as a photo-conversion voltage amplifier supported on the substrate formed with a threshold voltage of Vt0 having a gate terminal connected to the charge-integration node. The photodetector further includes a MOS transistor supported on the substrate functioning as a constant current-source load transistor having a drain terminal connected to a source terminal of the gate-biased charge storable n-type MOS transistor and a gate terminal connected to a bias reference voltage. The photodetector further includes a pre-charge switch transistor supported on the substrate having a source terminal connected to charge-integration node and a drain terminal connected to a bias voltage source. (The photodetector further includes a MOS transistor supported on the substrate functioning as a readout switch transistor having a source terminal connected to a drain terminal of the gate-biased charge storable n-type MOS transistor). In an alternate preferred embodiment, the photodetector is formed in a p-type substrate.

대표청구항 ▼

[I claim:] [1.]a p-n junction diode having a charge-integration node;a gate-biased charge storable MOS transistor having a gate terminal connected to the charge-integration node of said p-n junction diode;a readout switch MOS transistor connected to a source terminal of said charge storable MOS tran

[I claim:] [1.]a p-n junction diode having a charge-integration node;a gate-biased charge storable MOS transistor having a gate terminal connected to the charge-integration node of said p-n junction diode;a readout switch MOS transistor connected to a source terminal of said charge storable MOS transistor;a bias charge pre-charge switch MOS transistor connected to said charge-integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor;a second gate-biased charge storable MOS transistor;a second readout switch MOS transistor having a drain terminal connected to a source terminal of said second charge storable MOS transistor and a gate terminal connected to a gate terminal of said readout switch MOS transistor; anda second bias charge pre-charge switch MOS transistor having a gate terminal connected to a power supply bus Vdd, a drain terminal connected to said voltage reference and a source terminal connected to a gate terminal of said second gate-biased charge storable MOS transistor.