초록 ▼

An apparatus architecture is provided which permits an easily programmed apparatus (10) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (10) is connected to a communications bus (40) which receives apparatus parameter, topological

An apparatus architecture is provided which permits an easily programmed apparatus (10) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (10) is connected to a communications bus (40) which receives apparatus parameter, topological, and microinstruction information from a host processor and/or memory (EPROM). The apparatus includes numerous functional blocks (20), a core (30), and a parametric/microinstruction bus (35). The functional blocks include serial (62,66) and parallel ports (68), D/A (54) and A/D (52) converters, and programmable signal processors (300) which serve to process signal data and are connected in any desired manner through a switching matrix (160) located in the core. The topology of the switching matrix (160) is received via the communications bus (40). Parameters and microinstructions for the programmable signal processors (300) are sent via the communications bus (40), the core (30), and the parametric/microinstruction (35) bus. Topological and/or parametric data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held in programmable nonvolatile or volatile memory associated with the core and functional blocks. Signal data is typically received and transmitted via the serial and/or parallel ports (62,66,68) and via the D/A and A/D (54,52) converters of the apparatus. Each apparatus can be made part of a larger wafer-scale system including several identical or architecturally similar apparatus by providing links between the apparatus.

대표청구항 ▼

[What is claimed is:] [1.]a) a plurality of programmable signal processor means having means for receiving and storing parameters and microinstructions, and means for executing microinstructions, each said programmable signal processor means for performing an operation according to said microinstruc

[What is claimed is:] [1.]a) a plurality of programmable signal processor means having means for receiving and storing parameters and microinstructions, and means for executing microinstructions, each said programmable signal processor means for performing an operation according to said microinstructions and said parameters on signal data received by said programmable signal processor means;b) a core means comprising interface means for interfacing with said communications bus, decoder means for distinguishing between at least topological and parametric data received by said core means over said communications bus, and matrix switching means for interconnecting at least two of said plurality of programmable signal processor means in a desired manner in response to said topological data received over said communications bus;c) a plurality of data bus means for connecting said plurality of programmable signal processor means to said matrix switching means; andd) at least one third bus means coupled to said core means and to said means for receiving and storing, for transmitting said parametric data and said microinstructions to said means for receiving and storing of at least a plurality of said programmable signal processor means.