초록 ▼

A program controlled integrated circuit having an input path for receiving an analog signal with given attributes and using a program controlled sequence of treatment stages to generate a bit-defined information vector. That vector is introduced to a distributed memory matching array where it is com

A program controlled integrated circuit having an input path for receiving an analog signal with given attributes and using a program controlled sequence of treatment stages to generate a bit-defined information vector. That vector is introduced to a distributed memory matching array where it is compared with conveyed instruction set having bit-defned codewords corresponding with an analog signal attribute. A match process under the control of a central control unit then develops a digital result. The digital result may be utilized or converted to analog form in an analog return path. Both the input path and the return path incorporate a reduced instruction set computing arithmetic unit under the control of the central control unit.

대표청구항 ▼

[What is claimed is:] [1.]a conditioning stage connectable to receive said analog signal to provide a conditioned analog signal;an oversampling coder stage responsive to an oversampling control and to said conditioned analog signal to provide a corresponding coded serial bit stream output;a decimati

[What is claimed is:] [1.]a conditioning stage connectable to receive said analog signal to provide a conditioned analog signal;an oversampling coder stage responsive to an oversampling control and to said conditioned analog signal to provide a corresponding coded serial bit stream output;a decimating filter stage responsive to a decimating filter control and to said coded serial bit stream output to provide an output with a bit-defined information vector having a data aspect corresponding with said given signal attributes;an interface port having a coupling portion connectable for communication with said external control component and an internal portion;programming and data memory including a distributed memory matching array responsive to a conveyed instruction set having bit-defined codewords corresponding with a selected one of said signal attributes, responsive to a match control input to identify a correspondence between said information vector and at least one of said codewords to provide a digital result;an output network responsive to said digital result to derive an output signal; anda central control unit coupled in data exchange relationship with said interface port internal portion and said programming and data memory and responsive to derive said oversampling control, said decimating filter control, said match control input, and to effect conveyance of said instruction set to said distributed memory matching array.