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Precision trim circuit for delay lines

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-005/13
출원번호 US-0102730 (1998-06-22)
발명자 / 주소
  • Goetting F. Erich
  • Hyland Paul G.
  • Hassoun Joseph H.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Mao, Esq.
인용정보 피인용 횟수 : 50  인용 특허 : 5

초록

A precision trim circuit for a tuneable delay line is provided. The precision trim circuit provides delays greater than the base delay of the tuneable delay line. By using larger delays than conventional trim circuits, the precision trim circuit of the present invention can use components that react

대표청구항

[What is claimed is:] [1.]a delay line having a base delay; anda trim circuit coupled to the delay line and havinga first delay element having a first delay at least equal to the base delay of the delay line;a second delay element having a second delay greater than the first delay;a multiplexer coup

이 특허에 인용된 특허 (5)

  1. Parkinson Peter B. (Tigard OR), Active selectable digital delay circuit.
  2. Sato Yu,JPX, Delay circuit compensating for variations in delay time.
  3. Allen Michael J., Method and apparatus to reduce signal delay mismatch in a high speed interface.
  4. Yamauchi Shigenori (Kariya JPX) Watanabe Takamoto (Nagoya JPX), Programmable delay line programmable delay circuit and digital controlled oscillator.
  5. Fujii Haruhiko,JPX, Variable delay circuit.

이 특허를 인용한 특허 (50)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  6. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  7. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  8. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  9. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  10. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  11. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  12. Kaviani, Alireza S., DCVSL pulse width controller and system.
  13. Oh, Kwansuhk; Pang, Raymond C., Delay line trim unit having consistent performance under varying process and temperature conditions.
  14. Seshadri, Anand; Eliason, Jarrod R.; Jabillo, Edwin Cezar, Delay system for generating control signals in ferroelectric memory devices.
  15. Laszlo Goetz DE; Stefan Reithmaier DE; Martin Rommel DE, Digital driver circuit.
  16. Kim, Nam-Seog; Yoon, Yong-Jin, Digitally controllable internal clock generating circuit of semiconductor memory device and method for same.
  17. Tomita, Takashi, Display panel driving device having plural driver chips responsive to clock signal with stable duty ratio.
  18. Masleid, Robert P, Dynamic ring oscillators.
  19. Gomm,Tyler; Johnson,Gary, Graduated delay line for increased clock skew correction circuit operating range.
  20. Kaviani, Alireza S., Hard phase alignment of clock signals using asynchronous level-mode state machine.
  21. Kaviani, Alireza S., Hard phase alignment of clock signals with an oscillator controller.
  22. Salcido, Manuel; Yoh, Gilbert; Salcido, Jr., Salvador; Evans, Scott T., Internal bus termination technique for integrated circuits with local process/voltage/temperature compensation.
  23. Masleid, Robert P, Inverting zipper repeater circuit.
  24. Masleid, Robert P., Inverting zipper repeater circuit.
  25. Masleid, Robert Paul, Inverting zipper repeater circuit.
  26. Masleid, Robert, Leakage efficient anti-glitch filter.
  27. Kaviani, Alireza S.; Lynch, Patrick T.; Hyland, Paul G.; Crotty, Patrick J.; Pi, Tao, Method and apparatus for reducing jitter and power dissipation in a delay line.
  28. Kaviani, Alireza S., Method and apparatus for reducing jitter in a delay line and a trim unit.
  29. Gomm, Tyler; Johnson, Gary, Method and apparatus for synchronizing with a clock signal.
  30. Gomm, Tyler; Johnson, Gary, Methods and apparatus for synchronizing with a clock signal.
  31. Kaviani, Alireza S., Phase detector employing asynchronous level-mode sequential circuitry.
  32. Rosnell, Seppo, Phase modulating system.
  33. Masleid, Robert Paul, Power efficient multiplexer.
  34. Masleid, Robert Paul, Power efficient multiplexer.
  35. Masleid, Robert Paul, Power efficient multiplexer.
  36. Masleid, Robert Paul, Power efficient multiplexer.
  37. Masleid,Robert Paul, Power efficient multiplexer.
  38. Eken, Yalcin Alper; Katzin, Peter, RF detector with crest factor measurement.
  39. Eken, Yalcin Alper; Katzin, Peter, RF detector with crest factor measurement.
  40. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  41. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  42. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  43. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  44. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  45. Sartschev, Ronald A.; Walker, Ernest P., Strobe technique for recovering a clock in a digital signal.
  46. Sartschev, Ronald A.; Walker, Ernest P., Strobe technique for test of digital signal timing.
  47. Sartschev, Ronald A.; Walker, Ernest P., Strobe technique for time stamping a digital signal.
  48. Oh,Kwansuhk; Pang,Raymond C., Trim unit having less jitter.
  49. Matsunami, Hiroyuki, Variable delay circuit and delay amount control method.
  50. Kong,Cheng Gang; Suen,Victor, Wide-range programmable delay line.
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