초록 ▼

A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each tran

A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.

대표청구항 ▼

[What is claimed is:] [1.](a) defining a region of a silicon substrate for formation of a first field effect transistor with a first source and a first polysilicon gate adjacent a second field effect transistor with a second source and a second polysilicon gate, the first and second transistors shar

[What is claimed is:] [1.](a) defining a region of a silicon substrate for formation of a first field effect transistor with a first source and a first polysilicon gate adjacent a second field effect transistor with a second source and a second polysilicon gate, the first and second transistors sharing a common drain, the first and second polysilicon gates being spaced apart from one another to define a gap therebetween;(b) depositing a silicon dioxide layer on the region, the silicon dioxide layer covering the region and filling the gap defined between the first and second polysilicon gates;(c) removing a portion of the silicon dioxide layer by chemical mechanical polishing to expose a portion of the polysilicon gate for each of the pair of transistors to define a first surface;(d) etching the first and second polysilicon gates to define a first recess in the first polysilicon gate and a second recess in the second polysilicon gate;(e) establishing a photoresist pattern on the region, the photoresist pattern defining an opening over the common drain and at least a portion of the first recess;(f) selectively etching a portion of the silicon dioxide layer corresponding to the opening to define a third recess exposing at least a portion of the common drain;(g) removing the photoresist pattern;(h) covering the region with a metallic layer, the metallic layer filling the first, second, and third recesses;(i) planarizing the region by removing a portion of the metallic layer to define a second surface, the second surface including a first metallic region interconnecting the first gate and the common drain, a second metallic region provided by metal in the second recess, and an oxide region positioned between the first and second metallic regions; and(j) completing formation of the first and second field effect transistors.