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Bond pad design for integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0305766 (1999-05-05)
발명자 / 주소
  • Chittipeddi Sailesh
  • Ryan Vivian
출원인 / 주소
  • Lucent Technologies Inc.
인용정보 피인용 횟수 : 24  인용 특허 : 5

초록

The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support

대표청구항

[What is claimed is:] [1.]forming a first bond pad support layer located below said bond pad;forming an opening in said first bond pad support layer; andforming a second bond pad support layer on said first bond pad support layer and at least partially into said opening to form a bond pad support su

이 특허에 인용된 특허 (5)

  1. Chittipeddi Sailesh ; Cochran William Thomas ; Smooha Yehuda, Integrated circuit with active devices under bond pads.
  2. Freeman ; Jr. John L. (Mesa AZ) Tracy Clarence J. (Tempe AZ), Method for making a planar multi-layer metal bonding pad.
  3. Shiue Ruey-Yun (Hsin-Chu TWX) Wu Wen-Teng (Hsin-Chu TWX) Shieh Pi-Chen (Hsinchu TWX) Liu Chin-Kai (Hsin-Chu TWX), Method of forming bond pad structure for the via plug process.
  4. Heim Dorothy A. (San Jose CA), Semiconductor bond pads.
  5. Sato Hisakatsu,JPX, Semiconductor device having a multi-latered wiring structure.

이 특허를 인용한 특허 (24)

  1. Chen-Wen Tsai TW; Chung-Ju Wu TW; Wei-Feng Lin TW, Bond pad structure and its method of fabricating.
  2. Tsai, Chen-Wen; Wu, Chung-Ju; Lin, Wei-Feng, Bond pad structure and its method of fabricating.
  3. Kim, Kyoung-Hwan, Bonding pad structure and manufacturing method thereof.
  4. Shu, William Kuang-Hua, Die pad crack absorption system and method for integrated circuit chip fabrication.
  5. Righter,Alan W, Integrated circuit bond pad structures and methods of making.
  6. Righter,Alan W., Integrated circuit bond pad structures and methods of making.
  7. Kuo,Yian Liang; Lin,Yu Chang, Integrated circuit package bond pad having plurality of conductive members.
  8. Rhodes,Howard E., Local multilayered metallization.
  9. Ming-Dou Ker TW; Hsin-Chin Jiang TW, Low-capacitance bonding pad for semiconductor device.
  10. Batra, Shubneesh; Chaine, Michael D.; Keeth, Brent; Akram, Salman; Manning, Troy A.; Johnson, Brian; Martin, Chris G.; Merritt, Todd A.; Smith, Eric J., Method and structures for reduced parasitic capacitance in integrated circuit metallizations.
  11. Batra,Shubneesh; Chaine,Michael D.; Keeth,Brent; Akram,Salman; Manning,Troy A.; Johnson,Brian; Martin,Chris G.; Merritt,Todd A.; Smith,Eric J., Method and structures for reduced parasitic capacitance in integrated circuit metallizations.
  12. Pozder,Scott K.; Kobayashi,Thomas S., Method for forming a bond pad interface.
  13. Lee,Jin Hyuk; Kim,Gu Sung; Lee,Dong Ho; Jang,Dong Hyeon, Method for manufacturing a wafer level chip scale package.
  14. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  15. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  16. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  17. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  18. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  19. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  20. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  21. Kim, Jung Sam, Semiconductor device and method for forming the same.
  22. Minakshisundaran Balasubramanian Anand JP, Semiconductor device and method of manufacturing the same.
  23. Anand, Minakshisundaran Balasubramanian, Semiconductor device having a plurality of conductive layers.
  24. Chittipeddi, Sailesh; Merchant, Sailesh Mansinh, Wire bonding method for copper interconnects in semiconductor devices.
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