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Method of forming multiple levels of patterned metallization

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0237258 (1999-01-26)
발명자 / 주소
  • Buynoski Matthew S.
  • Lin Ming-Ren
출원인 / 주소
  • Advanced Micro Devices, Inc.
인용정보 피인용 횟수 : 51  인용 특허 : 15

초록

Submicron-dimensioned metallization patterns are formed on a substrate surface by a photo-activated selective, anisotropic etching process, wherein selective portions of a metal layer are exposed to collimated UV passing through a pattern of submicron-sized openings in an overlying exposure mask. At

대표청구항

[What is claimed is:] [1.](a) providing a substrate comprising a semiconductor wafer with a surface having a dielectric layer fonned thereover, said dielectric layer comprising a surface including a first in-laid metallization pattern including a plurality of spaced-apait metal features forming elec

이 특허에 인용된 특허 (15)

  1. Ogawa Toshiaki (Hyogo JPX), Apparatus for forming interconnection pattern.
  2. Douglas Monte A. (Coppell TX), Copper dry etch process using organic and amine radicals.
  3. Nishizawa Jun-ichi (Sendai JPX) Yamamoto Kenji (Chiba JPX), Dry etching method.
  4. Chen Lee (Poughkeepsie NY) Chuang Tung J. (Los Gatos CA) Mathad Gangadhara S. (Poughkeepsie NY), Laser induced dry chemical etching of metals.
  5. Loper Gary L. (Huntington Beach CA) Tabat Martin D. (Nashua NH), Method for patterning and etching film layers of semiconductor devices.
  6. Wang Mu-Chun,TWX, Method for preventing damage to gate oxide from well in complementary metal-oxide semiconductor.
  7. Tsujii Kanji (Nishitama JPX) Yajima Yusuke (Musashino JPX) Murayama Seiichi (Kokubunji JPX), Method of dry etching.
  8. Papadas Constantin,FRX, Method of forming interconnections in an integrated circuit.
  9. Kerber Martin,DEX ; Klose Helmut,DEX ; Vom Felde Andreas, Method of manufacturing semiconductor components.
  10. Jain Ajay, Process for forming a semiconductor device.
  11. Azuma Junzou (Yokohama JPX) Itoh Fumikazu (Fujisawa JPX) Haraichi Satoshi (Yokohama JPX) Shimase Akira (Yokohama JPX) Mori Junichi (Kodama-gun JPX) Takahashi Takahiko (Iruma JPX) Uda Emiko (Oume JPX), Processing method and apparatus using focused energy beam.
  12. Donelon John J. (Mahopac NY) Tomkiewicz Yaffa (Scarsdale NY) Wassick Thomas A. (Wappingers Falls NY) Yeh James T. (Katonah NY), Selective metal etching in metal/polymer structures.
  13. Engelsberg Audrey C. (Milton VT) Fitzpatrick Donna R. (Washington DC), Selective removal of material by irradiation.
  14. Gray David C. (Sunnyvale CA) Butterbaugh Jeffery W. (Chanhassen MN), UV-enhanced dry stripping of silicon nitride films.
  15. Lur Water (Taipei TWX) Chen Ben (Hsin-chu TWX), VLSI process with global planarization.

이 특허를 인용한 특허 (51)

  1. Chisholm, Michael F.; Edwards, Darvin R.; Hotchkiss, Gregory B.; Rincon, Reynaldo; Sundararaman, Viswanathan, Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers.
  2. Hirata,Akisuke; Isoda,Shinji; Kadowaki,Yutaka; Mushiake,Katsuhiko, Components for film forming device.
  3. Cheng Hsin-Li,TWX ; Yang Chang-Da,TWX ; Wang Ping-Wei,TWX, Damascene local interconnect process.
  4. Kordic, Srdjan; Roussel, C?line; Inard, Alain, Electrical connection device between two tracks of an integrated circuit.
  5. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.
  6. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
  7. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
  8. Farrar,Paul A., Hplasma treatment.
  9. Farrar, Paul A., Integrated circuit and seed layers.
  10. Farrar,Paul A., Integrated circuit and seed layers.
  11. Farrar,Paul A., Integrated circuit and seed layers.
  12. Efland, Taylor R.; Abbott, Donald C.; Bucksch, Walter; Corsi, Marco; Shen, Chi-Cheong; Erdeljac, John P.; Hutter, Louis N.; Mai, Quang X.; Wagensohner, Konrad; Williams, Charles E.; Buschbom, Milton , Integrated circuit with bonding layer over active circuitry.
  13. Jessie,Darryl; Persico,Charles J., Integrated circuit with low-loss primary conductor strapped by lossy secondary conductor.
  14. Su,Michael Zhuoying, Interconnect speed sensing circuitry.
  15. Clevenger,Lawrence; Hsu,Louis; Tyberg,Christy S.; Yuan,Tsorng Dih, Low dielectric semiconductor device and process for fabricating the same.
  16. Shemesh, Dror, Method and system for imaging a cross section of a specimen.
  17. Chine-Gie Lou TW, Method for forming inter metal dielectric.
  18. Sywert H. Brongersma BE; Emmanuel Richard FR; Iwan Vervoort BE; Karen Maex BE, Method for improving the quality of a metal layer deposited from a plating bath.
  19. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
  20. Yegnashankaran, Visvamohan; Padmanabhan, Gobi R., Method of forming a metal interconnect with capacitive structures that adjust the capacitance of the interconnect.
  21. Szczech, John B.; Gamota, Daniel R.; Klosowiak, Tomasz L.; Wielgus, Jerzy, Method to pattern metallized substrates using a high intensity light source.
  22. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  23. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  24. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  25. Chiang, Tony P.; Lazovsky, David E.; Boussie, Thomas R.; Gorer, Alexander, Methods for discretized formation of masking and capping layers on a substrate.
  26. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  27. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  28. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  29. Iwasaki, Akihisa; Takahashi, Michiya; Ueki, Akira; Chida, Chikako; Motojima, Dai, Multilayer interconnects with an extension part.
  30. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
  31. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  32. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  33. Yegnashankaran,Visvamohan; Padmanabhan,Gobi R., Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect.
  34. Shih, Chien Hsueh; Yu, Chen Hua, Process for low resistance metal cap.
  35. Shih,Chien Hsueh; Yu,Chen Hua, Process for making a metal seed layer.
  36. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
  37. Nakatani, Goro; Sakamoto, Tatsuya, Semiconductor device and method for manufacturing the same.
  38. Farrar, Paul A., Structures and methods to enhance copper metallization.
  39. Farrar, Paul A., Structures and methods to enhance copper metallization.
  40. Farrar, Paul A., Structures and methods to enhance copper metallization.
  41. Farrar,Paul A., Structures and methods to enhance copper metallization.
  42. Farrar,Paul A., Structures and methods to enhance copper metallization.
  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Shih, Chien-Hsueh; Shue, Shau-Lin, Transitional interface between metal and dielectric in interconnect structures.
  51. Shih, Chien-Hsueh; Shue, Shau-Lin, Transitional interface between metal and dielectric in interconnect structures.
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