초록 ▼

A circuit monitor performance of an integrated circuit. The circuit includes a clock signal and a phase delay detection circuit. The clock signal is used by the integrated circuit to generate an output signal on an output pin of the integrated circuit. The phase delay detection circuit detects relat

A circuit monitor performance of an integrated circuit. The circuit includes a clock signal and a phase delay detection circuit. The clock signal is used by the integrated circuit to generate an output signal on an output pin of the integrated circuit. The phase delay detection circuit detects relative phase difference between the clock signal and the output signal on the output pin of the integrated circuit. The phase delay detection circuit includes a digital signal generator and an integrator. The digital signal generator is connected to an output pin of the integrated circuit. The digital signal generator generates a digital signal. Changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal used by the integrated circuit are encoded in a duty cycle of the digital signal generated by the digital signal generator. The integrator is connected to the digital signal generator and integrates the digital signal to produce an integrated signal. A voltage level of the integrated signal indicates relative phase delay between the output signal and the clock signal.

대표청구항 ▼

[We claim:] [1.]a phase delay detection circuit coupled to an output pin of the integrated circuit and to a clock signal, the clock signal being used to clock circuitry within the integrated circuit, the circuitry within the integrated circuit generating an output signal on the output pin of the int

[We claim:] [1.]a phase delay detection circuit coupled to an output pin of the integrated circuit and to a clock signal, the clock signal being used to clock circuitry within the integrated circuit, the circuitry within the integrated circuit generating an output signal on the output pin of the integrated circuit, wherein the phase delay detection circuit includes:digital signal generating means, coupled to the output pin of the integrated circuit, for generating a digital signal, wherein changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal result in changes in a duty cycle of the digital signal generated by the digital signal generating means, wherein the digital signal generating means comprises:a delay flip-flop having a D input, a clock input and a Q output, the clock signal being coupled to the clock input and the output signal being coupled to the D input, anda gate having a signal input, a control input and an output, the output signal on the output pin of the integrated circuit being coupled to the signal input of the gate, and the Q output being coupled to the control input of the gate; andintegrating means for integrating the digital signal to produce an integrated signal, the integrated means having an input coupled to the output of the gate, wherein a voltage level of the integrated signal indicates relative phase delay between the output signal on the output pin of the integrated circuit and the clock signal.