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High speed digital signal processor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
출원번호 US-0143351 (1998-08-28)
우선권정보 KR0012318 (1998-04-07)
발명자 / 주소
  • Lim Il Taek,KRX
  • Bahn Jun Ho,KRX
  • Kim Kyu Seok,KRX
출원인 / 주소
  • LG Electronics Inc., KRX
대리인 / 주소
    Fleshner & Kim, LLP
인용정보 피인용 횟수 : 27  인용 특허 : 6

초록

A digital signal processor having an ALU and accumulating register small in bit number. The digital signal processor adds r-bit rounding bits to an N-bit data(wherein r

대표청구항

[What is claimed is:] [1.]data input means for receiving a N-bit data;rounding bit adding means for adding r-bit rounding bits to the N-bit data from the data input means, wherein r is smaller than N;guard bit adding means for adding g-bit guard bits to the high-order bits of the data from the round

이 특허에 인용된 특허 (6)

  1. Lamb Kenneth J. (Plympton GB2), Arithmetic logic and shift device.
  2. Im Jin Hyeock,KRX, Arithmetic operating device for digital signal processing and method therefor.
  3. Fujihara Shiro (Tokyo JPX), Barrel shifter.
  4. Satou Shigeki (Yokohama JPX) Sato Taizo (Kawasaki JPX), Blocks and bits sequence reversing device using barrel shift.
  5. Ishida Ryuji (Tokyo JPX) Kiuchi Toyoo (Tokyo JPX), Overflow correction circuit.
  6. Morikawa Toru,JPX ; Higaki Nobuo,JPX ; Miyoshi Akira,JPX ; Sumida Keizo,JPX, Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation proce.

이 특허를 인용한 특허 (27)

  1. Xiang,Shuhua; Yuan,Hongjun; Li,Sha, Address generation for video processing.
  2. Ford, Simon; Seal, David James, Aliasing data processing registers.
  3. Tessarolo, Alexander, Apparatus and method for saturating data in register.
  4. Xiang, Shuhua; Sha, Li; Luo, Yaojun, Cell array and method of multiresolution motion estimation and compensation.
  5. He,Ouyang; Sha,Li; Xiang,Shuhua; Zhu,Ping; Luo,Yaojun, DCT/IDCT with minimum multiplication.
  6. Langhammer, Martin, DSP processor architecture with write datapath word conditioning and analysis.
  7. Langhammer, Martin, DSP processor architecture with write datapath word conditioning and analysis.
  8. Rose,Andrew Christopher; Ford,Simon Andrew; Symes,Dominic Hugo; Seal,David James, Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a s.
  9. Ford,Simon Andrew; Symes,Dominic Hugo; Rose,Andrew Christopher; Lutz,David Raymond; Hinds,Christopher Neal, Data processing apparatus and method for moving data elements between a chosen lane of parallel processing in registers and a structure within memory.
  10. Ford,Simon Andrew; Symes,Dominic Hugo; Rose,Andrew Christopher; Lutz,David Raymond; Hinds,Christopher Neal, Data processing apparatus and method for moving data elements between specified registers and a continuous block of memory.
  11. Symes, Dominic Hugo; Ford, Simon Andrew, Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number.
  12. Symes, Dominic Hugo; Ford, Simon Andrew, Data processing apparatus and method for performing arithmetic operations in SIMD data processing.
  13. Ford, Simon Andrew; Seal, David James; Dijkstra, Wilco, Data processing apparatus and method for performing data processing operations on floating point data elements.
  14. Ford,Simon Andrew; Symes,Dominic Hugo, Data processing apparatus and method for performing in parallel a data processing operation on data elements.
  15. Morris,Chris, Data processor with enhanced instruction execution and method.
  16. Dupont de Dinechin,Beno?t, High-efficiency saturating operator.
  17. Dijkstra, Wilco; Ford, Simon Andrew; Seal, David James, Method and apparatus for constant generation in SIMD processing.
  18. Renno, Erik K.; Pedersen, Ronny; Strom, Oyvind, Method and apparatus for formatting numbers in microprocessors.
  19. Metzgen, Paul, Methods and apparatus for implementing a saturating multiplier.
  20. Wang, Xu; Xiang, Shuhua; Sha, Li, Multiple channel data bus control for video processing.
  21. Ouyang,He; Sha,Li; Xiang,Shuhua; Luo,Yaojun; Zeng,Weimin; Ding,Jun, Multiple format video compression.
  22. Xiang,Shuhua; Sha,Li; Zhu,Ping; Yuan,Hongjun; Ni,Wei, Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention.
  23. Clark, Martin; McLernon, Michael H., Reporting fixed-point information for a graphical model.
  24. Carpenter,Paul Matthew; Ford,Simon Andrew, Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register.
  25. Sha,Li; Xiang,Shuhua; Xu,Wang, System for video processing control and scheduling wherein commands are unaffected by signal interrupts and schedule commands are transmitted at precise time.
  26. Symes, Dominic Hugo; Ford, Simon; Rose, Andrew Christopher, Table lookup operation within a data processing system.
  27. Sha,Li; Xiang,Shuhua; Luo,Yaojun; Ouyang,He, Video input processor in multi-format video compression system.
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