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Silicon-on-insulator (SOI) substrate and method of fabricating the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/30
  • H01L-021/76
  • H01L-021/425
  • H01L-027/01
출원번호 US-0292948 (1999-04-16)
우선권정보 JP0108202 (1998-04-17)
발명자 / 주소
  • Ogura Atsushi,JPX
출원인 / 주소
  • NEC Corporation, JPX
대리인 / 주소
    Sughrue, Mion, Zinn, Macpeak & Seas, PLLC
인용정보 피인용 횟수 : 64  인용 특허 : 4

초록

There is provided a method of fabricating a silicon-on-insulator substrate, including the steps of (a) forming a silicon substrate at a surface thereof with an oxygen-containing region containing oxygen at such a concentration that oxygen is not precipitated in the oxygen-containing region in later

대표청구항

[What is claimed is:] [1.](a) forming a silicon substrate with an oxygen-containing region, wherein said oxygen-containing region contains oxygen at such a concentration that oxygen is not precipitated in said oxygen-containing region during heat treatment;(b) forming a silicon oxide film at a surfa

이 특허에 인용된 특허 (4)

  1. Lee Sahng Kyoo,KRX ; Park Sang Kyun,KRX, Method for fabricating semiconductor wafers.
  2. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Method for producing semiconductor substrate.
  3. Henley Francois J. ; Cheung Nathan W., Reusable substrate for thin film separation.
  4. Srikrishnan Kris V., Smart-cut process for the production of thin semiconductor material films.

이 특허를 인용한 특허 (64)

  1. Chrysler, Gregory M.; Watwe, Abhay A.; Agraharam, Sairam; Ravi, Kramadhati V.; Garner, Michael C., Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat.
  2. Chrysler, Gregory M.; Watwe, Abhay A.; Agraharam, Sairam; Ravi, Kramadhati V.; Garner, Michael C., Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat.
  3. Chrysler,Gregory M.; Watwe,Abhay A.; Agraharam,Sairam; Ravi,Kramadhati V.; Garner,Michael C., Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat.
  4. Chrysler,Gregory M.; Watwe,Abhay A.; Agraharam,Sairam; Ravi,Kramadhati V; Garner,Michael C., Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat.
  5. Bin Yu, Fabrication of fully depleted field effect transistor formed in SOI technology with a single implantation step.
  6. Couillard, James G.; Gadkaree, Kishor P.; Mach, Joseph F., Glass-based SOI structures.
  7. Couillard, James G.; Gadkaree, Kishor P.; Mach, Joseph F., Glass-based SOI structures.
  8. Couillard,James G.; Gadkaree,Kishor P.; Mach,Joseph F., Glass-based SOI structures.
  9. Couillard,James G.; Gadkaree,Kishor P.; Mach,Joseph F., Glass-based SOI structures.
  10. Couillard,James G.; Gadkaree,Kishor P.; Mach,Joseph F., Glass-based SOI structures.
  11. Couillard,James Gregory; Gadkaree,Kishor Purushottam; Mach,Joseph Frank, Glass-based SOI structures.
  12. Aitken,Bruce Gardiner; Dejneka,Matthew John; Gadkaree,Kishor Purushottam; Pinckney,Linda Ruth, High strain glass/glass-ceramic containing semiconductor-on-insulator structures.
  13. Czagas, Joseph A.; Woodbury, Dustin A.; Beasom, James D., Integrated circuit having a device wafer with a diffused doped backside layer.
  14. Czagas, Joseph A.; Woodbury, Dustin A.; Beasom, James D., Integrated circuit having a device wafer with a diffused doped backside layer.
  15. Czagas,Joseph A.; Woodbury,Dustin A.; Beasom,James D., Integrated circuit having a device wafer with a diffused doped backside layer.
  16. Gadkaree, Kishor Purushottam; Mayolet, Alexandre Michel, Large area semiconductor on glass insulator.
  17. Dang, Bing; Farinelli, Matthew; Knickerbocker, John; Prabhakar, Aparna; Trzcinski, Robert E.; Tsang, Cornelia K., Laser ablation of adhesive for integrated circuit fabrication.
  18. Kwon, Sung Ku; Cho, Young Kyun; Kim, Jong Dae, Manufacturing method of silicon on insulator wafer.
  19. Tsukamoto, Akira, Manufacturing method of solid-state image sensor.
  20. Joseph A. Czagas ; Dustin A. Woodbury ; James D. Beasom, Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide.
  21. Morimoto,Nobuyuki; Nishihata,Hideki, Method for producing SOI wafer.
  22. Okuda, Hidehiko; Kusaba, Tatsumi, Method for producing bonded wafer.
  23. Ravi,Kramadhati V., Method of fabricating a microelectronic die.
  24. Rayssac, Olivier; Rayssac, legal representative, Pierre; Rayssac, legal representative, Gisèle; Akatsu, Takeshi, Method of fabricating a release substrate.
  25. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  26. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  27. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  28. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  29. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  30. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  31. Czagas, Joseph A.; Woodbury, Dustin A.; Beasom, James D., Method of forming an integrated circuit having a device wafer with a diffused doped backside layer.
  32. Ravi, Kramadhati V.; Chrysler, Gregory M., Method of forming electronic dies wherein each die has a layer of solid diamond.
  33. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  34. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  35. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  36. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  37. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  38. Yamazaki, Shunpei, Method of manufacturing a semiconductor device having a gate electrode formed over a silicon oxide insulating layer.
  39. Yamazaki, Shunpei, Method of manufacturing a semiconductor device including thermal oxidation to form an insulating film.
  40. Yamazaki, Shunpei, Method of manufacturing semiconductor device having island-like single crystal semiconductor layer.
  41. Delprat,Daniel; Neyret,Eric; Kononchuk,Oleg; Reynaud,Patrick; Stinco,Michael, Methods for manufacturing compound-material wafers and for recycling used donor substrates.
  42. Schwarzenbach, Walter; Ben Mohamed, Nadia; Maleville, Christophe; Maunand Tussot, Corinne, Methods for minimizing defects when transferring a semiconductor useful layer.
  43. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Nonvolatile memory and electronic apparatus.
  44. Schwarzenbach, Walter; Maleville, Christophe, Process for detaching layers of material.
  45. Schwarzenbach,Walter; Maleville,Christophe, Process for detaching layers of material.
  46. Guiot, Eric; Lallement, Fabrice, Process for fabricating a substrate comprising a deposited buried oxide layer.
  47. Alexander Y Usenko ; William N. Carr, Process for lift off and transfer of semiconductor devices onto an alien substrate.
  48. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device.
  49. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device including the selective forming of porous layer.
  50. Riccobene, Concetta E.; Ju, Dong-Hyuk, SOI device with body recombination region, and method.
  51. Takao, Noriyuki, SOI substrate and method of manufacturing the same.
  52. Graef, Dieter; Blietz, Markus; Wahlich, Reinhold; Miller, Alfred; Zemke, Dirk, SOI wafer and method for producing it.
  53. Gr��f,Dieter; Blietz,Markus; Wahlich,Reinhold; Miller,Alfred; Zemke,Dirk, SOI wafer and method for producing it.
  54. Yoo, Woo Sik, Selective heating using flash anneal.
  55. Yamazaki, Shunpei, Semiconductor device.
  56. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Semiconductor device having buried oxide film.
  57. Gadkaree,Kishor Purushottam, Semiconductor on glass insulator made using improved ion implantation process.
  58. Couillard,James Gregory; Gadkaree,Kishor Purushottam, Semiconductor on glass insulator with deposited barrier layer.
  59. Cherekdjian, Sarko, Semiconductor structure made using improved multiple ion implantation process.
  60. Cherekdjian, Sarko, Semiconductor structure made using improved multiple ion implantation process.
  61. Cherekdjian, Sarko, Semiconductor structure made using improved pseudo-simultaneous multiple ion implantation process.
  62. Cherekdjian, Sarko, Semiconductor structure made using improved simultaneous multiple ion implantation process.
  63. Abe, Takao; Matsuura, Takashi; Murota, Junichi, Semiconductor wafer and method for producing the same.
  64. Aitken,Bruce Gardiner; Gadkaree,Kishor Purushottam; Dejneka,Matthew John; Pinckney,Linda Ruth, Strained semiconductor-on-insulator structures and methods for making strained semiconductor-on-insulator structures.
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