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Dual damascene process for carbon-based low-K materials 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0431536 (1999-10-29)
발명자 / 주소
  • Chen Chao-Cheng,TWX
  • Lui Ming-Huei,TWX
  • Liu Jen-Cheng,TWX
  • Chao Li-chih,TWX
  • Tsai Chia-Shiung,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufactuirng Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 48  인용 특허 : 11

초록

A method for forming a dual damascene structure in a carbon-based, low-K material. The process begins by providing a semiconductor structure having a first metal pattern thereover, wherein the first metal pattern has a first barrier layer thereon. An organic dielectric layer is formed on the first b

대표청구항

[What is claimed is:] [1.]a. providing a semiconductor structure having a first metal pattern thereover; said first metal pattern having a first barrier layer thereon;b. forming an organic dielectric layer on said first barrier layer;c. forming a hard mask layer on said organic dielectric layer;d. f

이 특허에 인용된 특허 (11)

  1. Tsai Meng-Jin,TWX ; Huang Yimin,TWX, Damascene process with anti-reflection coating.
  2. Grill Alfred ; Hummel John Patrick ; Jahnes Christopher Vincent ; Patel Vishnubhai Vitthalbhai ; Saenger Katherine Lynn, Dual damascene processing for semiconductor chip interconnects.
  3. Avanzino Steven (Cupertino CA) Gupta Subhash (San Jose CA) Klein Rich (Mountain View CA) Luning Scott D. (Menlo Park CA) Lin Ming-Ren (Cupertino CA), Dual damascene with a protective mask for via etching.
  4. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  5. Jain Ajay ; Lucas Kevin, Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC).
  6. Wu Juan-Yuan,TWX ; Lur Water,TWX, Method of fabricating a dual damascene structure in an integrated circuit.
  7. Shoda Naohiro (Wappingers Falls NY), Method of forming studs and interconnects in a multi-layered semiconductor device.
  8. Yoo Bong-Young,KRX ; Choi Si-Young,KRX, Methods of forming electrical interconnects on semiconductor substrates.
  9. Lu Zhijian ; Moreau Wayne, Silylation method for reducing critical dimension loss and resist loss.
  10. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.
  11. Yim Randy M., Simplified hole interconnect process.

이 특허를 인용한 특허 (48)

  1. Chen, Tze-Chiang; Engel, Brett H.; Fitzsimmons, John A.; Kane, Terence; Lustig, Naftall E.; McDonald, Ann; McGahay, Vincent; Seo, Soon-Cheon; Stamper, Anthony K.; Wang, Yun Yu; Kaltalioglu, Erdem, Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof.
  2. Chen, Tze-Chiang; Engel, Brett H.; Fitzsimmons, John A.; Kane, Terence; Lustig, Naftall E.; McDonald, Ann; McGahay, Vincent; Seo, Soon-Cheon; Stamper, Anthony K.; Wang, Yun Yu; Kaltalioglu, Erdem, Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof.
  3. Kumar,Kaushik; Clevenger,Lawrence; Dalton,Timothy; La Tulipe,Douglas C.; Cowley,Andy; Kaltalioglu,Erdem; Schacht,Jochen; Simon,Andrew H.; Hoinkis,Mark; Kaldor,Steffen K.; Yang,Chih Chao, Bilayered metal hardmasks for use in Dual Damascene etch schemes.
  4. Kumar,Kaushik; Clevenger,Lawrence; Dalton,Timothy; La Tulipe,Douglas C.; Cowley,Andy; Kaltalioglu,Erdem; Schacht,Jochen; Simon,Andrew H.; Hoinkis,Mark; Kaldor,Steffen K.; Yang,Chih Chao, Bilayered metal hardmasks for use in dual damascene etch schemes.
  5. Subramanian, Ramkumar; Grundke, Wolfram; Singh, Bhanwar; Lyons, Christopher F.; Plat, Marina V., Dual bake for BARC fill without voids.
  6. Chen, Meng-Hung; Shu, Yu-Sheng; Lo, Ming Hung; Lee, Chung-Yuan, Dual damascene process.
  7. Tu,Kuo Chi; Chen,Chun Yao; Chu,Huey Chi, Embedded DRAM for metal-insulator-metal (MIM) capacitor structure.
  8. Ishikawa, Mitsuru; Hagihara, Masaaki; Inazawa, Koichiro, Etching method.
  9. Takeuchi, Koichi, Fabrication method of semiconductor device.
  10. Wang,Yun Yu; Conti,Richard A.; Eng,Chung Ping; Nicholls,Matthew C., HDP-based ILD capping layer.
  11. Wang,Yun Yu; Conti,Richard A; Eng,Chung Ping; Nicholls,Matthew C, HDP-based ILD capping layer.
  12. America,William G.; Johnston,Steven H., Integrated dual damascene RIE process with organic patterning layer.
  13. Liu, Shih Chang; Liu, Yuan Hung; Tsai, Chia Shiung, Ladder poly etching back process for word line poly planarization.
  14. Liu, Yuan Hung; Wu, Chih Ta; Chao, Lan Lin; Tu, Yeur Luen; Lin, Wen Chin; Tsai, Chia Shiung, Magnetic memory cells and manufacturing methods.
  15. Liu,Yuan Hung; Wu,Chih Ta; Chao,Lan Lin; Tu,Yeur Luen; Lin,Wen Chin; Tsai,Chia Shiung, Magnetic memory cells and manufacturing methods.
  16. Hong, Liubo; Zhu, Honglin, Magnetoresistive device with a hard bias capping layer.
  17. Hiroshi Okamura JP, Manufacturing method for semiconductor device having a multilayer interconnect.
  18. Si, Weimin; Hong, Liubo; Zhu, Honglin; Yu, Winnie; Schmidt, Rowena, Method and system for providing a magnetoresistive structure using undercut free mask.
  19. Daniels, Brian J.; Dunne, Jude A.; Kennedy, Joseph T., Method for eliminating reaction between photoresist and OSG.
  20. Daniels, Brian J.; Dunne, Jude A.; Kennedy, Joseph T., Method for eliminating reaction between photoresist and OSG.
  21. Kim, Kwang-Ok, Method for fabricating saddle type fin transistor.
  22. Chine-Gie Lou TW, Method for forming a via and interconnect in dual damascene.
  23. Wang, Fei; Cheng, Jerry; Okada, Lynne A.; Tran, Minh Quoc; You, Lu, Method for forming dual damascene interconnect structure.
  24. Okada,Lynne A.; Wang,Fei; Kai,James, Method for forming inlaid structures for IC interconnections.
  25. Tsing-Fong Hwang TW; Tsung-Yuan Hung TW, Method for forming metal interconnection structure without corner faceted.
  26. Hiroshi Okamura JP, Method for manufacturing multilayer interconnects by forming a trench with an underlying through-hole in a low dielectric constant insulator layer.
  27. Park, Chang Soo, Method for manufacturing semiconductor device having porous low dielectric constant layer formed for insulation between metal lines.
  28. Park, Chang Soo, Method for manufacturing semiconductor device having porous low dielectric constant layer formed for insulation between metal lines.
  29. Yang, Danning; Luo, Guanghong; Li, Yun-Fei, Method for providing a magnetoresistive element having small critical dimensions.
  30. Hong, Liubo; Zhu, Honglin, Method for providing at least one magnetoresistive device.
  31. Tu, Kuo-Chi; Chen, Chun-Yao; Chu, Huey-Chi, Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure.
  32. Li, Lih-Ping; Lu, Hsin-Hsien; Jang, Syun-Ming, Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer.
  33. Lin, Chih-Han; Chen, Kun-Ei, Method of forming dual damascene semiconductor device.
  34. Fei Wang ; Lynne A. Okada ; Ramkumar Subramanian ; Calvin T. Gabriel, Method of making a dual damascene structure without middle stop layer.
  35. Fei Wang ; Lynne A. Okada ; Ramkumar Subramanian ; Calvin T. Gabriel, Method of making a slot via filled dual damascene structure with a middle stop layer.
  36. Li-Te Lin TW; Yuan-Hung Chiu TW; Ming-Huan Tsai TW; Hun-Jan Tao TW, Partial resist free approach in contact etch to improve W-filling.
  37. Liu, Chung-Shi; Shue, Shau-Lin, Prevention of post CMP defects in CU/FSG process.
  38. Celii, Francis G.; Xing, Guoqiang; McKerrow, Andrew; Ralston, Andrew; Tang, Zhicheng; Newton, Kenneth J.; Kraft, Robert; West, Jeff, Process flow for dual damescene interconnect structures.
  39. Chen, Chao Cheng; Yeh, Chen Nan, Process to reduce surface roughness of low K damascene.
  40. Mei Sheng Zhou SG; John Sudijono SG; Subhash Gupta SG; Sudipto Roy SG; Paul Ho SG; Xu Yi SG; Simon Chooi SG; Yakub Aliyu SG, Process without post-etch cleaning-converting polymer and by-products into an inert layer.
  41. Tu, Kuo-Chi, Self-aligned MIM capacitor process for embedded DRAM.
  42. Tu,Kuo Chi, Self-aligned MIM capacitor process for embedded DRAM.
  43. Yoshitaka, Hikaru, Semiconductor device and method of manufacturing the same.
  44. Watanabe,Kenichi; Komada,Daisuke; Shimpuku,Fumihiko, Semiconductor device with dual damascene wiring.
  45. Naoki Kasai JP, Semiconductor device with reduced number of intermediate level interconnection pattern and method of forming the same.
  46. Kloster,Grant; Leu,Jihperng; Wong,Lawrence; Ott,Andrew; Marrow,Patrick, Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer.
  47. Chou, Pei Yu; Huang, Chun Jen, Structure of metal interconnect and fabrication method thereof.
  48. Chou,Pei Yu; Huang,Chun Jen, Structure of metal interconnect and fabrication method thereof.
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