초록 ▼

A dual damascene process for producing interconnects. The dual damascene process includes forming an etching stop layer over a substrate having a conductive layer therein, and forming an inter-layer dielectric layer over the etching stop layer. A mask layer is formed over the dielectric layer. The m

A dual damascene process for producing interconnects. The dual damascene process includes forming an etching stop layer over a substrate having a conductive layer therein, and forming an inter-layer dielectric layer over the etching stop layer. A mask layer is formed over the dielectric layer. The mask layer and the inter-layer dielectric layer are patterned to form an opening that expose a portion of the etching stop layer. The opening is formed above the conductive layer. Photoresist material is deposited over the mask layer and into the opening. The photoresist layer and the mask layer are patterned, and the photoresist material inside the opening is turned into a photoresist plug at the same time. A top layer of the photoresist plug is removed. Using the patterned photoresist layer and the mask layer as a mask, an anisotropic etching step is carried out to form a plurality of trenches inside the inter-layer dielectric layer. These trenches overlap with the opening. Metal is finally deposited into the opening and the trenches to complete the dual damascene process.

대표청구항 ▼

[What is claimed is:] [1.]providing a substrate having a conductive layer therein;forming an etching stop layer over the substrate and the conductive layer;forming an inter-layer dielectric layer over the etching stop layer;forming a mask layer over the inter-layer dielectric layer;patterning the ma

[What is claimed is:] [1.]providing a substrate having a conductive layer therein;forming an etching stop layer over the substrate and the conductive layer;forming an inter-layer dielectric layer over the etching stop layer;forming a mask layer over the inter-layer dielectric layer;patterning the mask layer and the inter-layer dielectric layer to form an opening that exposes a portion of the etching stop layer inside the inter-layer dielectric layer such that the opening is located directly above the conductive layer;depositing photoresist material on the mask layer and into the opening;patterning the photoresist layer and the mask layer such that the photoresist material inside the opening forms a photoresist plug;performing a removing operation to remove a top layer of the photoresist plug;performing an anisotropic etching operation with the patterned photoresist layer and the mask layer serving as a mask so as to form a plurality of trenches in the inter-layer dielectric layer such that the trenches overlap with the opening;removing substantially the entirety of the remaining photoresist layer;removing the etching stop layer exposed in the opening and the mask layer; anddepositing metal into the trenches and the opening.