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Methods for making copper and other metal interconnections in integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0032197 (1998-02-27)
발명자 / 주소
  • Ahn Kie Y.
  • Forbes Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 40  인용 특허 : 36

초록

A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Yet, aluminum wires have greater electrical resistance and are less reliable than copper wires. Unfortunately, current techniques for making copper wires are time-

대표청구항

[What is claimed is:] [1.]forming a hole or trench in a layer of the integrated-circuit assembly;forming a first diffusion barrier inside the hole or trench;forming a second diffusion barrier on the layer adjacent the hole or trench through jet-vapor deposition of a diffusion-barring material; andat

이 특허에 인용된 특허 (36)

  1. Bruni Marie-Dominique,FRX, Anode for a flat display screen.
  2. Douglas Monte A. (Coppell TX), Copper dry etch process using organic and amine radicals.
  3. Joshi Rajiv Vasant ; Tejwani Manu Jamnadas ; Srikrishnan Kris Venkatraman, High aspect ratio low resistivity lines/vias by surface diffusion.
  4. Jin Shu ; Mu Xiao Chun ; Chen Xing ; Bourget Lawrence, High density plasma physical vapor deposition.
  5. Nakano Tadashi (Chiba JPX) Ono Hideaki (Chiba JPX), Interconnection structure for semiconductor integrated circuit and manufacture of the same.
  6. Kapoor Ashok K. (Palo Alto CA) Pasch Nicholas F. (Pacifica CA), Low dielectric constant insulation layer for integrated circuit structure and method of making same.
  7. Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
  8. Zhou Mei Sheng,SGX ; Ron-Fu Chu,SGX, Method for chemical-mechanical polish (CMP) planarizing of cooper containing conductor layers.
  9. Svendsen Leo Gulvad (Redwood City CA) Walker Clifford James (Fremont CA) Lykins ; II James Leborn (San Jose CA), Method for electroplating a substrate containing an electroplateable pattern.
  10. Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
  11. Geusic Joseph E. ; Forbes Leonard ; Ahn Kie Y., Method for forming high capacitance memory cells.
  12. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
  13. Fiordalice Robert ; Garcia Sam ; Ong T. P., Method of decreasing resistivity in an electrically conductive layer.
  14. Hong Qi-Zhong ; Jeng Shin-Puu ; Hsu Wei-Yung, Method of forming diffusion barriers encapsulating copper.
  15. Canaperi Donald F. (Bridgewater CT) Jagannathan Rangarajan (Patterson NY) Krishnan Mahadevaiyer (Hopewell Junction NY), Method of replenishing electroless gold plating baths.
  16. Carey David H. (Austin TX), Methods of forming channels and vias in insulating layers.
  17. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  18. Schmitt ; III Jerome J. (New Haven CT) Halpern Bret L. (Bethany CT), Microwave plasma assisted supersonic gas jet deposition of thin film materials.
  19. Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers.
  20. Havemann Robert H. ; Stoltz Richard A., Process for conductors with selective deposition.
  21. Misawa Nobuhiro (Kawasaki JPX), Process for fabricating integrated circuit devices.
  22. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
  23. Tobin Philip J. ; Hegde Rama I. ; Tseng Hsing-Huang ; O'Meara David ; Wang Victor, Process for forming a semiconductor device.
  24. Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY), Process for making multilayer integrated circuit substrate.
  25. Tokunaga Takafumi (Tokorozawa JPX) Tsuneoka Masatoshi (Ohme JPX) Mizukami Koichiro (Akishima JPX), Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device.
  26. Awaya Nobuyoshi (Isehara JPX) Arita Yoshinobu (Isehara JPX), Process for selectively growing thin metallic film of copper or gold.
  27. Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and h.
  28. Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
  29. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  30. Clampitt Darwin A., Semiconductor circuit interconnections and methods of making such interconnections.
  31. Hughes Henry G. (Scottsdale AZ) Lue Ping-Chang (Scottsdale AZ) Robinson Frederick J. (Scottsdale AZ), Semiconductor device having a low permittivity dielectric.
  32. Shirk Albert (Palmyra PA) Ceresa Myron (Advance NC), Sensitized polyimides and circuit elements thereof.
  33. Yao Gongda ; Ding Peijun ; Xu Zheng ; Kieu Hoa, Silicon-doped titanium wetting layer for aluminum plug.
  34. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  35. Young Peter L. (South Barrington IL) Cech Jay (Elmhurst IL) Li Kin (Lombard IL), Thin-film electrical connections for integrated circuits.
  36. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (40)

  1. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  2. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  3. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  4. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  5. Ahn, Kie Y; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  6. Ahn,Kie Y; Forbes,Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  7. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using enhanced reflow.
  8. Farrar, Paul A., Copper metallurgy in integrated circuits.
  9. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.
  10. Farrar, Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
  11. Farrar,Paul A., Hplasma treatment.
  12. Farrar, Paul A., Integrated circuit and seed layers.
  13. Farrar,Paul A., Integrated circuit and seed layers.
  14. Farrar,Paul A., Integrated circuit and seed layers.
  15. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
  16. Shinichi Hoshi JP, Method of fabricating semiconductor device.
  17. Gardes,Pascal; Auriel,G��rard, Method of manufacturing an inductance.
  18. Chen, Fusen; Chen, Ling; Glenn, Walter Benjamin; Gopalraja, Praburam; Fu, Jianming, Methods and apparatus for forming barrier layers in high aspect ratio vias.
  19. Chen, Fusen; Chen, Ling; Glenn, Walter Benjamin; Gopalraja, Praburam; Fu, Jianming, Methods and apparatus for forming barrier layers in high aspect ratio vias.
  20. Chen, Fusen; Chen, Ling; Glenn, Walter Benjamin; Gopalraja, Praburam; Fu, Jianming, Methods and apparatus for forming barrier layers in high aspect ratio vias.
  21. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  22. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  23. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  24. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  25. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  26. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  27. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
  28. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  29. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  30. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
  31. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
  32. Choi, Eun Young; Baek, Eun Jin, Semiconductor device having load resistor and method of fabricating the same.
  33. Higashi, Kazuyuki; Takase, Tamao; Shibata, Hideki, Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure.
  34. Farrar, Paul A., Structures and methods to enhance copper metallization.
  35. Farrar, Paul A., Structures and methods to enhance copper metallization.
  36. Farrar, Paul A., Structures and methods to enhance copper metallization.
  37. Farrar,Paul A., Structures and methods to enhance copper metallization.
  38. Farrar,Paul A., Structures and methods to enhance copper metallization.
  39. Tang, Yu-Po; Chang, Shih-Ming; Hsieh, Ken-Hsien; Liu, Ru-Gun, Via-free interconnect structure with self-aligned metal line interconnections.
  40. Matsubara, Yoshihisa; Okada, Norio, Wiring structure in a semiconductor device.
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