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Semiconductor chip package with fan-in leads

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0739303 (1996-10-29)
발명자 / 주소
  • Fjelstad Joseph
  • Karavakis Konstantine
출원인 / 주소
  • Tessera, Inc.
대리인 / 주소
    Lerner, David, Littenberg, Krumholz & Mentlik
인용정보 피인용 횟수 : 167  인용 특허 : 22

초록

A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or "assembly", contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The complian

대표청구항

[What is claimed is:] [1.]a semiconductor chip having a plurality of peripheral chip contacts on a face surface thereof and a central region bounded by the peripheral chip contacts;a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface o

이 특허에 인용된 특허 (22)

  1. Matsuda Tatsuharu (Kawasaki JPX) Minamizawa Masaharu (Kawasaki JPX), Bump electrode, semiconductor integrated circuit device using the same, multi-chip module having the semiconductor integ.
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  3. Patraw Nils E. (Redondo Beach CA), Compressive pedestal for microminiature connections.
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  8. Nelson Gregory H. (Gilbert AZ), Method of manufacturing an interconnect device having coplanar contact bumps.
  9. Distefano Thomas H. (Monte Sereno CA) Kovac Zlata (Los Gatos CA) Grange John (Cupertino CA), Microelectronic bonding with lead motion.
  10. Distefano Thomas H. (Monte Sereno CA) Kovac Zlata (Los Gatos CA) Grange John (Cupertino CA), Microelectronic bonding with lead motion.
  11. DiStefano Thomas H. (Monte Sereno CA) Smith ; Jr. John W. (Austin TX), Microelectronics unit mounting with multiple lead bonding.
  12. Schreiber Christopher M. (Newport Beach CA) Crumly William R. (Anaheim CA), Resilient interconnection bridge.
  13. Karavakis Konstantine ; Fjelstad Joseph, Semiconductor assemblies with reinforced peripheral regions.
  14. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies having interposer and flexible lead.
  15. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with fan-in leads.
  16. Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Semiconductor chip assemblies, methods of making same and components for same.
  17. DiStefano, Thomas H.; Grube, Gary W.; Khandros, Igor Y.; Mathiew, Gaetan, Semiconductor connection components and method with releasable lead support.
  18. Nishimura Hiroyuki (Hyogo JPX) Adachi Hiroshi (Hyogo JPX) Adachi Etsushi (Hyogo JPX) Yamamoto Shigeyuki (Hyogo JPX) Minami Shintaro (Hyogo JPX) Harada Shigeru (Hyogo JPX) Tajima Toru (Hyogo JPX) Hagi, Semiconductor device having a multilayer interconnection structure.
  19. Aoyama Masaharu (Fujisawa JPX) Abe Masahiro (Yokohama JPX) Ajima Takashi (Kamakura JPX) Yonezawa Toshio (Kitakyushu JPX), Semiconductor device having a multilayer wiring structure using a polyimide resin.
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  22. Palagonia Anthony Michael, Wafer with elevated contact structures.

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