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Interactive dubug tool for programmable circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H02H-003/05
출원번호 US-0976750 (1997-11-24)
발명자 / 주소
  • Guccione Steven A.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Cartier
인용정보 피인용 횟수 : 96  인용 특허 : 13

초록 ▼

An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configurat

대표청구항 ▼

[What is claimed is:] [1.]means for specifying a logic cell in the logic device to be probed;means for reading configuration data from the specified logic cell; andmeans for displaying a graphical representation of logic in the logic device implemented by the configuration data from the specified lo

이 특허에 인용된 특허 (13)

  1. Sample Stephen P. (Mountain View CA) D\Amour Michael R. (Los Altos Hills CA) Payne Thomas S. (Union City CA), Apparatus for emulation of electronic hardware system.
    상세보기
  2. Ranson Gregory L. ; Brockmann Russell C. ; Naas Robert E., Circuitry and method for detecting signal patterns on a bus using dynamically changing expected patterns.
    상세보기
  3. Casselman Steven M., Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed.
    상세보기
  4. Lawman Gary R. (San Jose CA) Wells Robert W. (Cupertino CA), Concurrent electronic circuit design and implementation.
    상세보기
  5. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
    상세보기
  6. Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.
    상세보기
  7. Lynch John (Austin TX) Franke David (Austin TX), Method and apparatus for configuring systems.
    상세보기
  8. Lynch John ; Franke David, Method and apparatus for configuring systems.
    상세보기
  9. Patel Chandresh (3480 Granada Ave. ; #249 Santa Clara CA 95051), Method and apparatus to emulate VLSI circuits within a logic simulator.
    상세보기
  10. Dangelo Carlos (Los Gatos CA) Watkins Daniel (Los Altos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
    상세보기
  11. Guccione Steven A., Network configuration of programmable circuits.
    상세보기
  12. Beatty Paul E. ; D'Arcy Paul G. ; Deschler Lee E. ; Prasad Mohit K., System and method for debugging digital signal processor software with an architectural view and general purpose comput.
    상세보기
  13. Cantone Michael R. (Westfield NJ) Woo Nam-Sung (New Providence NJ), System for synthesizing field programmable gate array implementations from high level circuit descriptions.
    상세보기

이 특허를 인용한 특허 (96)

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