초록 ▼

A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, eac

A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, each IC block being used to form a plurality of IC components such as memory cells. A multi-layer interconnect structure is formed to electrically interconnect these IC components in each of the IC blocks. A first testing and repair process is then perform to disconnect any inoperative IC components from active use. This completes the fabrication stage of the manufacture process. In the subsequent packaging stage, a redistribution line structure is formed to interconnect the discrete IC blocks into an integral functional unit. A second testing and repair process is then perform to disconnect any inoperative IC blocks from active use. The overall IC manufacture would have an increased yield as compared to the prior art.

대표청구항 ▼

[ What is claimed is:] [1.]1. A wafer level IC structure, which comprises:a semiconductor wafer;a plurality of discrete IC blocks defined on the wafer, each IC block including:a plurality of IC components and backup components;a multi-layer interconnect structure for electrically interconnecting the

[ What is claimed is:] [1.]1. A wafer level IC structure, which comprises:a semiconductor wafer;a plurality of discrete IC blocks defined on the wafer, each IC block including:a plurality of IC components and backup components;a multi-layer interconnect structure for electrically interconnecting the IC components in the associated IC block;a first set of bonding pads which are electrically connected to the multilayer interconnect structure and serve as external connecting points for the IC components in the associated IC block and for use during testing;a first set of fuses which are electrically connected to the IC components and the multi-layer interconnect structure for use to selectively disconnect the associated IC components from active use if the associated IC components are determined to be inoperative during testing;a redistribution line structure including a plurality of redistribution lines which are electrically connected to the first set of bonding pads of each of the IC blocks in a predefined manner so as to functionally combine the discrete IC blocks into an integral functional unit;a second set of bonding pads which are electrically connected to the IC blocks and the redistribution line structure for use to apply test signals to the IC blocks during testing; anda second set of fuses which are electrically connected to the redistribution line structure for use to selectively disconnect the associated IC blocks if the associated IC blocks are determined to be inoperative during testing.