초록 ▼

A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval,

A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.

대표청구항 ▼

[ What is claimed is:] [1.]1. A sensing apparatus for sensing a logic state stored in a memory cell, said memory cell having an associated bit-line and an associated word-line, wherein when said memory cell is accessed by an address which selects said associated bit-line and said associated word-lin

[ What is claimed is:] [1.]1. A sensing apparatus for sensing a logic state stored in a memory cell, said memory cell having an associated bit-line and an associated word-line, wherein when said memory cell is accessed by an address which selects said associated bit-line and said associated word-line, a voltage corresponding to said logic state is sensed by said sensing apparatus, said apparatus comprising:a means for comparing voltages having a sensing input and a reference signal input;a means for establishing a reference voltage on said reference signal input;a means for detecting a signal transition which occurs prior to the selection of said associated bit-line and said associated word-line and generating a detection pulse;a means for pre-charging said sensing input of said comparing means in response to said detection pulse to a voltage essentially equivalent to said reference voltage, said pre-charge means being disabled when said associated bit-line and said associated word-line have been selected;a means for establishing said voltage corresponding to said logic state of said memory cell on said sensing input of said comparing means when said associated bit-line and associated word-line have been selected;wherein said comparing means outputs a signal representing said logic state of said memory cell after said associated bit-line and associated word-line have been selected; whereinsaid pre-charging means includes a first circuit branch having a first set of loading devices coupled between a first working potential and said sensing input including a first sub-set of loading devices and a second sub-set of loading devices, wherein said second sub-set of loading devices are enabled once said detection pulse is generated and are disabled after said associated bit-line and associated word-line are selected; andsaid reference voltage means includes a second circuit branch having a second set of loading devices coupled between said first working potential and said reference signal input;wherein once said detection pulse is generated and when said associated bit-line and associated word-line are selected, said first and second sets of loading devices are essentially electrically equivalent.