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The present invention discloses a register file in which a read access time is reduced, a data bus width is made expandable, more rapid decoding can be given at a time of data readout, and the whole logic unit is made higher in performance. For these purposes, in the register file of the invention,

The present invention discloses a register file in which a read access time is reduced, a data bus width is made expandable, more rapid decoding can be given at a time of data readout, and the whole logic unit is made higher in performance. For these purposes, in the register file of the invention, register arrays are classified into a plurality of banks, and a sense amplifier is provided for each of the banks. Further, the register file includes a decoder to select a word corresponding to a result of decoding of partial bits of a read address so as to read the word from the register array in each of the banks, a decoder to specify a bank corresponding to a result of decoding of remaining bits of the read address, and a multiplexer to select the word from the bank specified by the decoder so as to output the word to the read port. The present invention can be applied to a storage portion mounted in a processing unit such as microprocessor or CPU to contain intermediate results of a calculation, constants, and so forth.

대표청구항 ▼

[ What is claimed is:] [10.]10. A register file, comprisingregister arrays having a multiport configuration in which a read port and a write port are mounted and read accesses and write accesses independently and concurrently are made through the ports, the register arrays being classified into bank

[ What is claimed is:] [10.]10. A register file, comprisingregister arrays having a multiport configuration in which a read port and a write port are mounted and read accesses and write accesses independently and concurrently are made through the ports, the register arrays being classified into banks every predetermined number of words;sense amplifiers respectively provided for the banks;an in-bank word selecting decoder, directly connected to each bank, to decode partial bits of an address specifying a word to be read, and to select a word corresponding to a result of decoding so as to read the word from the register array in each of the banks;a bank selecting decoder to decode remaining bits of the address so as to specify a bank corresponding to a result of decoding; anda multiplexer, coupled to the banks and to the bank selecting decoder, to take the word selected by the in-bank selecting decoder and amplified by the sense amplifier from each bank, and to select a word from the bank specified by the bank selecting decoder from among the words input by the banks and output the word to the read port.