|국가/구분||United States(US) Patent 등록|
|국제특허분류(IPC7판)||G06F-012/08 G06F-009/26 G11C-007/00|
|미국특허분류(USC)||711/127 ; 712/022 ; 365/189.02|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 57 인용 특허 : 6|
The present invention discloses a register file in which a read access time is reduced, a data bus width is made expandable, more rapid decoding can be given at a time of data readout, and the whole logic unit is made higher in performance. For these purposes, in the register file of the invention, register arrays are classified into a plurality of banks, and a sense amplifier is provided for each of the banks. Further, the register file includes a decoder to select a word corresponding to a result of decoding of partial bits of a read address so as to r...
[ What is claimed is:] [10.]10. A register file, comprisingregister arrays having a multiport configuration in which a read port and a write port are mounted and read accesses and write accesses independently and concurrently are made through the ports, the register arrays being classified into banks every predetermined number of words;sense amplifiers respectively provided for the banks;an in-bank word selecting decoder, directly connected to each bank, to decode partial bits of an address specifying a word to be read, and to select a word corresponding...