초록 ▼

A method and system for computing using a reconfigurable computer architecture utilizing programmable logic devices is disclosed. The computing may be accomplished by configuring a first programmable logic unit as a system controller. The system controller directs the implementation of an algorithm

A method and system for computing using a reconfigurable computer architecture utilizing programmable logic devices is disclosed. The computing may be accomplished by configuring a first programmable logic unit as a system controller. The system controller directs the implementation of an algorithm in a second one of the programmable logic units concurrently with reconfiguring a third one of the programmable logic units. In another aspect, the computing system may include a pair of independent, bi-directional busses each of which is arranged to electrically interconnect the system controller and the plurality of programmable logic devices. With this arrangement, a first bus may be used to reconfigure a selected one of the programmable logic devices as directed by the system controller while the second bus is used by an operational one of the programmable logic devices.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method of computing using a first independently programmable integrated circuit and a second independently programmable integrated circuit, said method comprising:configuring a first portion of the first integrated circuit as a controller;implementing an algorithm uti

[ What is claimed is:] [1.]1. A method of computing using a first independently programmable integrated circuit and a second independently programmable integrated circuit, said method comprising:configuring a first portion of the first integrated circuit as a controller;implementing an algorithm utilizing a second portion of the second integrated circuit, the implementation of the algorithm being directed by the first portion of the first integrated circuit operating as the controller, wherein, as needed, a third portion of the second integrated circuit is configured to operate as the controller in place of or in conjunction with the first portion of the first integrated circuit; andreconfiguring a fourth portion of the first integrated circuit concurrently with the implementing of the algorithm in the second portion of the second integrated circuit, the reconfiguring of the fourth portion of the first integrated circuit being directed by the first portion of the first integrated circuit operating as the controller, or by the third portion acting as the controller, wherein the first and the second integrated circuits are interconnected by a bi-directional bus, such that, as needed, any appropriate portion of either the first or the second integrated circuit can be reconfigured as needed.