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Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
출원번호 US-0385524 (1999-08-30)
발명자 / 주소
  • Chan Lap
  • Chew Johnny Kok Wai,SGX
  • Cha Cher Liang,SGX
  • Chua Chee Tee,SGX
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd., SGX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 33  인용 특허 : 8

초록

A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is d

대표청구항

[ What is claimed is:] [1.]1. A method of fabricating an inductor in the fabrication of an integrated circuit device comprising:forming a field oxide region in and on a semiconductor substrate;removing said field oxide region whereby a well is left in said semiconductor substrate;depositing a polish

이 특허에 인용된 특허 (8)

  1. Manning Monte, Integrated circuitry having a pair of adjacent conductive lines.
  2. Merrill Richard Billings ; Archer Donald M., Integrated inductor.
  3. Su Shyang,TWX ; Sheu Jeng Tzong,TWX ; Chuang Kuen Joung,TWX, Membrane type integrated inductor and the process thereof.
  4. Yu Hyun-Kyu,KRX ; Park Min,KRX, Method for forming an inductor devices using substrate biasing technique.
  5. Chu Shau-Fu Sanford,SGX ; Chew Kok Wai Johnny,SGX ; Chua Chee Tee,SGX ; Cha Cher Liang,SGX, Method of making spiral-type RF inductors having a high quality factor (Q).
  6. Abidi Asad A. (Los Angeles CA) Chang James Y.-C. (Los Angeles CA), Monolithic passive component.
  7. Hebert Francois, Semiconductor device having a passive device formed over one or more deep trenches.
  8. Jaouen Herve,FRX ; Marty Michel,FRX, Semiconductor device having separated exchange means.

이 특허를 인용한 특허 (33)

  1. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  2. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
  3. Acosta, Raul E.; Lund, Jennifer L.; Groves, Robert A.; Rosner, Joanna; Cordes, Steven A.; Carasso, Melanie L., High Q inductor with faraday shield and dielectric well buried in substrate.
  4. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  5. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  6. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  7. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
  8. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
  9. Inoue, Akira; Gotou, Seiki, High power semiconductor device having source electrodes connected by air bridges and having opposite current path directions.
  10. Shuming Xu ; Hanhua Feng SG; Pang Dow Foo SG; Bai Xu ; Uppili Sridhar SG, Integrated circuit inductor.
  11. Tang, Jinbang; Frear, Darrel R.; Wenzel, Robert J., Integrated circuit module with integrated passive device.
  12. Ahn, Kie Y.; Forbes, Leonard, Low loss high Q inductor.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  15. Kim, Gu Sung, Method for manufacture of wafer level package with air pads.
  16. Xu, Shuming; Feng, Hanhua; Foo, Pang Dow; Xu, Bai; Sridhar, Uppili, Method of making an integrated circuit inductor wherein a plurality of apertures are formed beneath an inductive loop.
  17. Wang, Ruonan; Liu, Yan; He, Song; Wang, Tingting, Multiple surface integrated devices on low resistivity substrates.
  18. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  19. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  20. Durham, James A.; Kamekona, Keith; Schoonover, Brian, Semiconductor device and method of providing regions of low substrate capacitance.
  21. Hiroshi Yoshida JP, Semiconductor device having improved parasitic capacitance and mechanical strength.
  22. Grivna,Gordon M., Semiconductor device having reduced capacitance to substrate and method.
  23. Davies,Robert B., Semiconductor device with inductive component and method of making.
  24. Arne W. Ballantine ; Robert A. Groves ; Michael B. Rice ; Anthony K. Stamper, Spiral inductor semiconducting device with grounding strips and conducting vias.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  31. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  32. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
  33. Kim,Gu Sung, Wafer level package with air pads and manufacturing method thereof.
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