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Semiconductor device having programmable interconnect layers 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/10
출원번호 US-0621432 (1996-03-25)
발명자 / 주소
  • Lee Ji-Min
  • Santandrea Joseph F.
  • Lien Chuen-Der
  • Hansen Anita
  • Perham Leonard
출원인 / 주소
  • Integrated Device Technology, Inc.
대리인 / 주소
    Bever Hoffman & Harms, LLP
인용정보 피인용 횟수 : 70  인용 특허 : 15

초록

An integrated circuit structure is described which includes a base semiconductor structure and a programmable semiconductor structure which are fabricated separately and later joined to form the integrated circuit structure. The base semiconductor structure includes conventional semiconductor device

대표청구항

[ We claim:] [1.]1. An integrated circuit structure comprising:a base semiconductor structure, wherein active and passive regions are located in the base semiconductor structure; anda programmable semiconductor structure formed separately from the base semiconductor structure and joined to the base

이 특허에 인용된 특허 (15)

  1. Williams Ronald L. (San Marcos CA) Tyra Joe B. (Carlsbad CA), Apparatus and method for protecting metal bumped integrated circuit chips during processing and for providing mechanical.
  2. Takada Norimasa (Tokyo JPX), Flip chip type semiconductor device.
  3. Tanizawa Tetsu (Kawasaki JPX), Integrated circuit semiconductor device formed on a wafer.
  4. Delgado Jose Avelino ; Gaul Stephen Joseph, Integrated circuit with an air bridge having a lid.
  5. Carlomagno William D. (Redwood City CA) Cummings Dennis E. (Placerville CA) Gliga Alexandru S. (San Jose CA), Interconnection of electronic components.
  6. Balyoz John (Hopewell Junction NY) Chang Chi S. (Wappingers Falls NY) Fox Barry C. (Poughkeepsie NY) Palmieri John A. (Wappingers Falls NY) Ghafghaichi Majid (Poughkeepsie NY) Jen Teh-Sen (Fishkill N, Master image chip organization technique or method.
  7. Wilson Arthur M. (Richardson TX), Method for producing an integrated circuit product having a polyimide film interconnection structure.
  8. Tracy ; John M., Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components.
  9. Jacobs Scott L. (Apex NC), Method of making a extended integration semiconductor structure.
  10. Kaw Ravindhar K. (San Jose CA), Monolithic semiconductor chip interconnection technique and arrangement.
  11. Gupta Debabrata (Scottsdale AZ) Drye James E. (Mesa AZ), Multiple integrated circuit module which simplifies handling and testing.
  12. Santadrea Joseph F. (Los Altos Hills CA) Lee Ji-Min (Palo Alto CA) Lien Chuen-Der (Mountain View CA) Huggins Alan H. (Gilroy CA), Parallel manufacturing of semiconductor devices and the resulting structure.
  13. Hiki Yoshimasa (Tokyo JPX), Process of forming input/output wiring areas for semiconductor integrated circuit.
  14. Gordon Kathryn E. (Mountain View CA) Wong Richard J. (Milpitas CA), Programmable interconnect structures and programmable integrated circuits.
  15. Chang Mike F. ; Owyang King ; Hshieh Fwu-Iuan ; Ho Yueh-Se ; Dun Jowei, Surface mount and flip chip technology for total integrated circuit isolation.

이 특허를 인용한 특허 (70)

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  5. Hadley, Mark A.; Carrender, Curt L.; Smith, John Stephen; Craig, Gordon S. W., Assembly comprising a functional device and a resonator and method of making same.
  6. Hadley,Mark A.; Carrender,Curt L.; Smith,John Stephen; Craig,Gordon S. W., Assembly comprising a functional device and a resonator and method of making same.
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  9. Poechmueller, Peter, Backside of chip implementation of redundancy fuses and contact pads.
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  16. Kurita, Yoichiro; Soejima, Koji; Kawano, Masaya, Electronic circuit chip, and electronic circuit device and method for manufacturing the same.
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  20. Kazuhisa Miyamoto JP; Ryo Yamagata JP; Takayuki Uda JP, Input-output circuit cell and semiconductor integrated circuit apparatus.
  21. Fischer, Armin; Von Glasow, Alexander, Integrated circuit with pads connected by an under-bump metallization and method for production thereof.
  22. Yu, Chen-Hua; Jeng, Shin-Puu; Hou, Shang-Yun; Yeh, Der-Chyang, Interposer system and method.
  23. Phoon,Hee Kong; Yap,Kian Chin, Mask-programmable logic device with programmable input/output ports.
  24. Toshiaki Oda JP, Memory package implementing two-fold memory capacity and two different memory functions.
  25. Harshfield, Steven T., Method and apparatus for forming an integrated circuit electrode having a reduced contact area.
  26. Harshfield, Steven T., Method and apparatus for forming an integrated circuit electrode having a reduced contact area.
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  28. Yen, Wei-Kuo; Hsu, Yi-Chin; Chen, Cheng-Che; Chen, Chiu-Ju, Method and system for efficiently coordinating orders with product materials progressing through a manufacturing flow.
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  33. Marr, Kenneth W.; Batra, Shubneesh, Method of anti-fuse repair.
  34. Credelle, Thomas Lloyd; Gengel, Glenn; Stewart, Roger Green; Joseph, William Hill, Method of making a radio frequency identification (RFID) tag.
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  36. Abbott, Todd; Trivedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.
  37. Christiansen, Cathryn J.; Norfleet, Andrew H.; Peterson, Kirk D.; Turner, Andrew A., Method of self-correcting power grid for semiconductor structures.
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  66. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  67. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  68. Carrender,Curt, Transponder incorporated into an electronic device.
  69. Caletka,David Vincent; Park,Seungbae; Sathe,Sanjeev Balwant, Wafer scale thin film package.
  70. Jacobsen,Jeffrey Jay; Gengel,Glenn Wilhelm; Hadley,Mark A.; Craig,Gordon S. W.; Smith,John Stephen, Web process interconnect in electronic assemblies.
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