초록 ▼

The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is o

The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is operable over a range of voltages (e.g., a range from below 3 volts to a range over 5 volts) without producing unbalanced operation of n-channel and p-channel transistors. Thus, integrated circuits formed in accordance with the present invention can be operated at different voltage power sources without requiring a redesign or relay out of the integrated circuit. In accordance with the present invention, CMOS transistors can be fabricated without increased fabrication complexity to provide transistors which operate within a relatively safe region of their operating characteristics and which operate with a speed that is unaffected by the reduced voltage supply (i.e., no need to accommodate timing errors since both n-channel and p-channel transistor performance remains balanced).

대표청구항 ▼

[ What is claimed is:] [1.]1. An integrated circuit comprising:at least one n-channel transistor having a gate, a source and a drain;at least one p-channel transistor having a gate, a source and a drain;at least one spacer located adjacent the gate of said n-channel transistor; andat least one addit

[ What is claimed is:] [1.]1. An integrated circuit comprising:at least one n-channel transistor having a gate, a source and a drain;at least one p-channel transistor having a gate, a source and a drain;at least one spacer located adjacent the gate of said n-channel transistor; andat least one additional spacer located adjacent the gate of said p-channel transistor, said at least one additional spacer being different in size than the at least one spacer of said n-channel transistor, a relative size of said at least one spacer and said at least one additional spacer being selected to provide balanced operation of said n-channel transistor and said p-channel transistor in response to a variation in voltage of a voltage power source of said n-channel and p-channel transistors wherein said at least one additional spacer has a height substantially equal to a height of said at least one spacer.