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Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/823.4
  • H01L-021/31
  • H01L-021/469
출원번호 US-0523988 (2000-03-13)
발명자 / 주소
  • Yu Mo-Chiun,TWX
  • Chen Wei-Ming,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 49  인용 특허 : 9

초록

A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation region. The substrate is first nitrided. Then t

대표청구항

[ What is claimed is:] [1.]1. A method of forming multiple oxide thicknesses with one step comprising the steps of:providing a substrate having a first active area and a second active area separated by a trench isolation region;performing nitridation to form a nitride layer over said substrate inclu

이 특허에 인용된 특허 (9)

  1. Lin Jengping (Taoyuan Hsien TWX), Method for fabricating gate oxide layers of different thicknesses.
  2. Doyle Brian ; Lee Jack, Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit.
  3. Buller James F. ; Fulford ; Jr. H. Jim, Method for growing dual oxide thickness using nitrided oxides for oxidation suppression.
  4. Tsui Paul G. Y. ; Tseng Hsing-Huang ; Bhat Navakanta ; Chen Ping, Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region.
  5. Soleimani Hamid R. (Westborough MA) Doyle Brian S. (Framingham MA) Philipossian Ara (Redwood Shores CA), Method of controlling gate oxide thickness in the fabrication of semiconductor devices.
  6. Nakata Hidetoshi (Tokyo JPX), Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation.
  7. Ibok Effiong E., Methodology for achieving dual gate oxide thicknesses.
  8. Chang Yun,TWX ; Shone Fuchia,TWX ; Huang Chih Mu,TWX ; Sung Kuo Tung,TWX, Nitridation process with peripheral region protection.
  9. Holloway Thomas C. ; Hattangady Sunil V., Semiconductor device having dual gate and method of formation.

이 특허를 인용한 특허 (49)

  1. Moore, John T.; DeBoer, Scott J., Capacitors.
  2. Moore,John T.; DeBoer,Scott J., Capacitors, methods of forming capacitors, and methods of forming capacitor dielectric layers.
  3. Ki Jae Huh KR; Duk Hee Lee KR, Fabrication method of semiconductor device.
  4. Kim, Sung-Hoan, Fabrication of semiconductor devices having high-voltage MOS transistors and low-voltage MOS transistors.
  5. Kim, Hyeon-Seag, High voltage oxidation method for highly reliable flash memory devices.
  6. Lim,Sangwoo; Kang,Laegu; Yeap,Geoffrey (Choh Fei), Integration of multiple gate dielectrics by surface protection.
  7. Lee,Seung Cheol; Park,Sang Wook; Song,Pil Geun, Method for forming isolation layer in semiconductor memory device.
  8. Chen, Rong-Ching; Huang, Ching-Chun; Lin, Jy-Hwang, Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage.
  9. Chen, Rong-Ching; Huang, Ching-Chun; Lin, Jy-Hwang, Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage.
  10. Krishnan, Anand T.; Reddy, Vijay, Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process.
  11. Suzuki, Tatsuya; Aoki, Hidemitsu, Method for manufacturing semiconductor device and semiconductor device.
  12. Pu, Shih-Chieh; Chiang, Ping-Hung; Hsiung, Chang-Po; Wang, Chia-Lin; Li, Nien-Chung; Lee, Wen-Fang; Hsiao, Shih-Yin; Wang, Chih-Chung; Liu, Kuan-Lin, Method of fabricating semiconductor MOS device.
  13. Moore, John T.; DeBoer, Scott J., Method of forming a capacitor dielectric layer.
  14. Sandhu, Gurtej S.; Moore, John T.; Rueger, Neal R., Method of forming a nitrogen-enriched region within silicon-oxide-containing masses.
  15. Beaman, Kevin L.; Moore, John T., Method of forming a structure over a semiconductor substrate.
  16. Beaman, Kevin L.; Moore, John T., Method of forming a structure over a semiconductor substrate.
  17. Beaman,Kevin L.; Moore,John T., Method of forming a structure over a semiconductor substrate.
  18. Moore, John T., Method of forming transistors associated with semiconductor substrates comprising forming a nitrogen-comprising region across an oxide region of a transistor gate.
  19. Nakagawa, Shinichi, Method of manufacturing semiconductor device.
  20. Ryoo, Doo Yeol, Method of manufacturing semiconductor devices using nitrification.
  21. Sandhu,Gurtej S.; Moore,John T.; Rueger,Neal R., Methods of forming a nitrogen enriched region.
  22. Moore, John T.; DeBoer, Scott J., Methods of forming capacitors.
  23. Eppich,Denise M.; Beaman,Kevin L., Methods of forming capacitors and methods of forming capacitor dielectric layers.
  24. Moore, John T., Methods of forming dielectric materials and methods of processing semiconductor substrates.
  25. Moore, John T., Methods of forming oxide regions over semiconductor substrates.
  26. Moore, John T., Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices.
  27. Beaman, Kevin L.; Moore, John T., Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates.
  28. Beaman,Kevin L.; Moore,John T., Methods of forming transistors.
  29. Sandhu,Gurtej S.; Moore,John T.; Rueger,Neal R., Methods of forming transistors.
  30. Moore, John T., Methods of forming transistors associated with semiconductor substrates.
  31. Sandhu, Gurtej S.; Moore, John T.; Rueger, Neal R., Methods of incorporating nitrogen into silicon-oxide-containing layers.
  32. Misium George R. ; Hattangady Sunil V., Nitridation for split gate multiple voltage devices.
  33. Chin, Pin-Shyne, Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device.
  34. Chin,Pin Shyne, Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device.
  35. Hao Fang ; Yue-song He, Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process.
  36. Wolstenholme, Graham R.; Helm, Mark A., Reduction of field edge thinning in peripheral devices.
  37. Wolstenholme,Graham R; Helm,Mark A, Reduction of field edge thinning in peripheral devices.
  38. Wolstenholme,Graham R; Helm,Mark A, Reduction of field edge thinning in peripheral devices.
  39. Beaman, Kevin L.; Moore, John T., Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates.
  40. Moore,John T., Semiconductor constructions.
  41. Koichi Ando JP, Semiconductor device having gate insulating layers different in thickness and material and process for fabrication thereof.
  42. Masuoka, Sadaaki, Semiconductor device including gate insulation films having different thicknesses.
  43. Masuoka, Sadaaki, Semiconductor device including gate insulation films having different thicknesses.
  44. Hakey, Mark Charles; Holmes, Steven John; Horak, David Vaclav; Koburger, III, Charles William; Mitchell, Peter H.; Nesbit, Larry Alan, Shallow trench isolation fill by liquid phase deposition of SiO.
  45. Underwood, Travis, Tracked mobility device.
  46. Underwood, Travis, Tracked mobility device.
  47. Moore, John T., Transistor devices.
  48. Sandhu,Gurtej S.; Moore,John T.; Rueger,Neal R., Transistor structures.
  49. Sandhu, Gurtej S.; Moore, John T.; Rueger, Neal R., Transistor structures, methods of incorporating nitrogen into silicon-oxide-containing layers; and methods of forming transistors.
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