초록 ▼

A computer system, bus interface unit employing a memory controller, and method are presented for optimizing the bandwidth data, address, and control transfer rates across a memory bus coupled to an SDRAM system. The SDRAM system is partitioned such that one partition will undergo pre-charge or refr

A computer system, bus interface unit employing a memory controller, and method are presented for optimizing the bandwidth data, address, and control transfer rates across a memory bus coupled to an SDRAM system. The SDRAM system is partitioned such that one partition will undergo pre-charge or refresh in the interim between times in which another partition (or a pair of partitions) initiate a burst read. The burst read cycles coincide with an initial column address of the burst, and are spaced a number of cycles equal to the burst length. Proper spacing of the initial column address, or read request, relative to a non-read requested partition ensures data read from the activated partition will be placed on the memory data bus in seamless fashion. That is, there are no non-data transfers occurring between data burst cycles, even though refresh or pre-charge operations are performed on a non-read partition. Careful placement of the hidden refresh cycles encountered by one partition relative to read cycles on other partitions ensures the data flow resulting therefrom will be optimized to sustain peak bandwidth on a synchronous DRAM memory bus.

대표청구항 ▼

[ What is claimed is:] [10.]10. A synchronous DRAM system, comprising:a clocking circuit coupled to produce a sequence of clocking cycles;a first set of synchronous DRAM integrated circuits coupled to the clocking circuit for reading a data burst of N clocking cycles initiated from a first read requ

[ What is claimed is:] [10.]10. A synchronous DRAM system, comprising:a clocking circuit coupled to produce a sequence of clocking cycles;a first set of synchronous DRAM integrated circuits coupled to the clocking circuit for reading a data burst of N clocking cycles initiated from a first read request;a second set of synchronous DRAM integrated circuits coupled to the clocking circuit for reading a data burst of N clocking cycles initiated from a second read request that occurs N clocking cycles after the first read request, wherein the first set of synchronous DRAM integrated circuits is further coupled to read a data burst of N clocking cycles initiated from a third read request that occurs N clocking cycles after the second read request; anda third set of synchronous DRAM integrated circuits coupled to initiate and culminate a sequence of refresh cycles in the interim between the second read request and the third read request.