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Transparent extended state save 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
출원번호 US-0961681 (1997-10-31)
발명자 / 주소
  • Christie David S.
  • Kranich Uwe,DEX
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Conley, Rose & Tayon, PCKowert
인용정보 피인용 횟수 : 31  인용 특허 : 57

초록 ▼

A microprocessor having a standard register set and an extended register set, which is configured to save its state upon suspension of either an extended register process or a standard register processor. The microprocessor is configured to execute both standard register instruction sequences and ex

대표청구항 ▼

[ What is claimed is:] [1.]1. A microprocessor, comprising:a microprocessor core, including:a standard register file; andan extended register file;wherein said microprocessor core is configured to execute standard instructions that use said standard register file, but not said extended register file

이 특허에 인용된 특허 (57)

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  1. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for conditional instruction execution.
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  2. Henry, G. Glenn; Hooker, Rodney E.; Parks, Terry, Apparatus and method for extending a microprocessor instruction set.
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  3. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for extending a microprocessor instruction set.
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  4. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for extending data modes in a microprocessor.
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  5. Henry, G. Glenn; Hooker, Rodney E.; Parks, Terry, Apparatus and method for instruction-level specification of floating point format.
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  6. Itou, Shigeki, Apparatus and method for processing an instruction that selects between single and multiple data stream operations with register specifier field control.
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  7. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor.
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  8. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for selective control of condition code write back.
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  9. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for selective control of results write back.
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  10. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for selective memory attribute control.
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  11. Bittner, Jr., Ray A.; Ginsberg, Michael, Dynamic address windowing on a PCI bus.
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  12. Kling, Ralph M, Extended register space apparatus and methods for processors.
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  13. Gschwind, Michael Karl; Montoye, Robert K.; Olsson, Brett; Wellman, John-David, Implementing instruction set architectures with non-contiguous register file specifiers.
    상세보기
  14. Bigbee, Bryant; Reneris, Kenneth S.; Kaushik, Shivnandan D., Maintaining extended and traditional states of a processing unit in task switching.
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  15. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Mechanism for extending the number of registers in a microprocessor.
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  16. Kahn, Opher D.; Peleg, Alexander; Valentine, Bob, Method and apparatus to support an expanded register set.
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  17. Kahn,Opher D.; Peleg,Alexander; Valentine,Bob, Method and apparatus to support an expanded register set.
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  18. Morris, Dale, Method and system for application managed context switching.
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  19. Parks, Terry; Henry, G. Glenn, Microprocessor that fuses if-then instructions.
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  20. Barlow,Stephen; Bailey,Neil; Ramsdale,Timothy; Plowman,David; Swann,Robert, Narrow/wide cache.
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  21. Henry, G. Glenn; Hooker, Rodney E.; Parks, Terry, Non-temporal memory reference control mechanism.
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  22. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Non-temporal memory reference control mechanism.
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  23. Hays, W. Patrick, Register set extension for compressed instruction set.
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  24. Henry, Glenn; Hooker, Rodney; Parks, Terry, Selective interrupt suppression.
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  25. McCrary, Rex Eldon; Mantor, Michael J.; Ashkar, Alexander Fuad; Wise, Harry J., Software control of state sets.
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  26. Boyle, Patrick; Keppel, David; Klaiber, Alex; Kelly, Edmund, Software direct memory access.
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  27. Henry, G. Glenn; Hooker, Rodney E.; Parks, Terry, Suppression of store checking.
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  28. Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Suppression of store checking.
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  29. Uwe Kranich DE; David S. Christie, System and method for transparent handling of extended register states.
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  30. Machida,Hiroyuki; Shinohara,Takao, Systems and methods for ensuring atomicity of processes in a multitasking computing environment.
    상세보기
  31. Kranich, Uwe, Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system.
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