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System and method for bonding over active integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0347212 (1999-07-02)
발명자 / 주소
  • Saran Mukul
출원인 / 주소
  • Texas Instruments Incorporated
대리인 / 주소
    Honeycutt
인용정보 피인용 횟수 : 80  인용 특허 : 2

초록 ▼

An architecture and method of fabrication for an integrated circuit having a reinforced bond pad comprising at least one portion of the integrated circuit disposed under the bond pad; and this at least one circuit portion comprises at least one dielectric layer and a patterned electrically conductiv

대표청구항 ▼

[ What is claimed is:] [1.]1. An integrated circuit comprising:a wire bonded terminal pad;at least one portion of said integrated circuit disposed under said bond pad; andsaid portion comprising at least one dielectric layer and a patterned electrically conductive reinforcing structure disposed in s

이 특허에 인용된 특허 (2)

  1. Cave Nigel G. ; Yu Kathleen C. ; Farkas Janos, Integrated circuit having a support structure.
    상세보기
  2. Owada Nobuo (Ohme JPX) Oogaya Kaoru (Ohme JPX) Kobayashi Tohru (Iruma JPX) Kawaji Mikinori (Hino JPX), Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wir.
    상세보기

이 특허를 인용한 특허 (80)

  1. Kang, Seung H.; Krebs, Roland P.; Steiner, Kurt George; Ayukawa, Michael C.; Merchant, Sailesh Mansinh, Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures.
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  2. Tsao, Pei-Haw; Lin, Liang-Chen; Niu, Pao-Kang; Liu, I-Tai; Kiang, Bill, Bond pad design to minimize dielectric cracking.
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  3. Chen-Hua Yu TW; Tsu Shih TW, Bond pad having variable density via support and method for fabrication.
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  4. Jeng, Shin-Puu; Liu, Yu-Wen; Tsai, Hao-Yi; Chen, Hsien-Wei, Bond pad structure.
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  5. Hsia, Chin Chiu; Yao, Chih Hsiang; Huang, Tai Chun; Peng, Chih Tang, Bond pad structure for wire bonding.
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  6. Huang,Tai Chun; Lee,Tze Liang, Bonding pad and via structure design.
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  7. Cho,Tai Heui; Kang,Hyuck Jin; Kim,Min Chul; Kim,Byung Yoon, Bonding pad structure of a semiconductor device.
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  8. Cho, Tai-Heui; Kang, Hyuck-Jin; Kim, Min-Chul; Kim, Byung-Yoon, Bonding pad structure of a semiconductor device and method for manufacturing the same.
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  9. Liu, Chung; Liu, Yuan-Lung; Shiue, Ruey-Yun, Bonding pad structure to minimize IMD cracking.
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  10. Liu,Chung; Liu,Yuan Lung; Shiue,Ruey Yun, Bonding pad structure to minimize IMD cracking.
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  11. Hichri,Habib; Liu,Xiao H.; McGahay,Vincent J.; Murray,Conal E.; Nayak,Jawahar P.; Shaw,Thomas M., Building metal pillars in a chip for structure support.
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  12. Hichri,Habib; Liu,Xiao H.; McGahay,Vincent J.; Murray,Conal E.; Nayak,Jawahar P.; Shaw,Thomas M., Building metal pillars in a chip for structure support.
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  13. Subhash Gupta SG; Mei Sheng Zhou SG; Ramasamy Chockalingam SG, CMP process utilizing dummy plugs in damascene process.
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  18. Pon, Harry Q., EMI and noise shielding for multi-metal layer high frequency integrated circuit processes.
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  23. Kärkkäinen, Asta Maria; Haque, Samiul Md; Colli, Alan; Pasanen, Pirjo Marjaana; Kärkkäinen, Leo Mikko Johannes; Uusitalo, Mikko Aleksi; Lehtiniemi, Reijo Kalervo, Graphene device and method of fabricating a graphene device.
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  26. Vo, Nhat D.; Tran, Tu-Anh N.; Carpenter, Burton J.; Hong, Dae Y.; Miller, James W.; Phillips, Kendall D., Integrated circuit having pads and input/output (I/O) cells.
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  29. Angell, David; Beaulieu, Frederic; Hisada, Takashi; Kelly, Adreanne; McKnight, Samuel Roy; Miyai, Hiromitsu; Petrarca, Kevin Shawn; Sauter, Wolfgang; Volant, Richard Paul; Weinstein, Caitlin W., Internally reinforced bond pads.
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  30. Angell,David; Beaulieu,Frederic; Hisada,Takashi; Kelly,Adreanne; McKnight,Samuel Roy; Miyai,Hiromitsu; Petrarca,Kevin Shawn; Sauter,Wolfgang; Volant,Richard Paul; Weinstein,Caitlin W., Internally reinforced bond pads.
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  31. Wang, Ping-Chuan; Brelsford, Kevin H.; Filippi, Ronald, Low dielectric constant material reinforcement for improved electromigration reliability.
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