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Component-based analog and mixed-signal simulation model development including newton step manager

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0305238 (1999-05-04)
발명자 / 주소
  • Mantooth H. Alan
  • Cooper Douglas K.
  • Vlach Martin
출원인 / 주소
  • Avant! Corporation
대리인 / 주소
    Skjerven, Morrill MacPhersonSuryadevara
인용정보 피인용 횟수 : 45  인용 특허 : 8

초록

The Model Editor (106) makes simulation modeling easier and more intuitive by extracting essential information and presenting it to the user, and by providing tools to investigate simulation and model robustness, in an interactive, graphical environment. The Model Editor (106) includes a Newton step

대표청구항

[ We claim:] [1.]1. A Newton step manager software tool for use in creating and revising a representation of a simulation model for modeling analog and mixed signal digital-analog physical circuits and systems in a digital computer, the Newton step manager software tool comprising:means for measurin

이 특허에 인용된 특허 (8)

  1. Gibbs Bruce P. ; Porter David W. ; Yancey William E., Apparatus and method for fusing diverse data.
  2. Kodosky Jeffrey L. (Austin TX) Truchard James J. (Austin TX) MacCrisken John E. (Palo Alto CA), Graphical method for programming a virtual instrument.
  3. Kodosky Jeffrey L. (Austin TX) Truchard James J. (Austin TX) MacCrisken John E. (Palo Alto CA), Graphical system for executing a process and for programming a computer to execute a process, including graphical variab.
  4. Kodosky Jeffrey L. (Austin TX) Truchard James J. (Austin TX) MacCrisken John E. (Palo Alto CA), Graphical system for modelling a process and associated method.
  5. Kodosky Jeffrey L. (Austin TX) Truchard James J. (Austin TX) MacCrisken John E. (Palo Alto CA), Graphical system for modelling a process and associated method.
  6. Konno Chisato (Inagi JPX) Ohata: Tadashi (Higashimurayama JPX) Igai Mitsuyoshi (Hino JPX) Umetani Yukio (Hachioji JPX) Yamabe Michiru (Hino JPX), Method for automatically generating a simulation program for a physical phenomenon governed by a partial differential eq.
  7. Kodosky Jeffrey L. (Austin TX) Truchard James J. (Austin TX) MacCrisken John E. (Palo Alto CA), Polymorphic dataflow block diagram system and method for programming a computer.
  8. Smith David W. (Forest Grove OR) Nolan Kevin P. (Tigard OR) Bayley Garland J. (Portland OR), Translation of behavioral modeling properties into an analog hardware description language.

이 특허를 인용한 특허 (45)

  1. Cragun, Brian J.; Grev, Christine A.; Rath, Cale T., Annotation structure type determination.
  2. Orfali,Marwan A.; Bauman,Mitchell A.; Kim,Myoungran, Apparatus and method for analyzing performance of a data processing system.
  3. Dettinger, Richard Dean; Johnson, Peter John; Stevens, Richard Joseph; Tong, Ikhua; Will, Eric, Application portability and extensibility through database schema and query abstraction.
  4. Suzuki, Kei; Ara, Koji; Yano, Kazuo, Computer readable medium with definition of interface recorded thereon, verification method for feasibility to connect given circuit and method of generating signal pattern.
  5. Suzuki, Kei; Ara, Koji; Yano, Kazuo, Computer readable medium with definition of interface recorded thereon, verification method for feasibility to connect given circuit and method of generating signal pattern.
  6. Fuxman, Adrian Matias; Pachner, Daniel, Condition-based powertrain control system.
  7. Stewart, Greg; Borrelli, Francesco; Pekar, Jaroslav, Configurable automotive controller.
  8. Stewart, Greg; Pekar, Jaroslav; Pachner, Daniel, Coordinated engine and emissions control system.
  9. Wheeler, William R.; Adiletta, Matthew J., Displaying information relating to a logic design.
  10. Vreugdenhil, Gordon J.; Christen, Ernst; Vlach, Martin, Dynamic association of equations to unknowns during simulations of systems described by hardware description languages.
  11. Dettinger, Richard D.; Kolz, Daniel P., Dynamic discovery of abstract rule set required inputs.
  12. Dong, He; Chui, Michael Z.; Yuan, Shan, Electronic circuit simulation method with adaptive iteration.
  13. Wheeler, William R.; Fennell, Timothy J.; Adiletta, Matthew J., Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture.
  14. Pachner, Daniel; Pekar, Jaroslav, Engine and aftertreatment optimization system.
  15. Stewart, Gregory E.; Rhodes, Michael L., Engine controller.
  16. Masella, Jr., Anthony; Webster, Bruce A., Facilitating comparisons between simulated and actual behavior of electronic devices.
  17. Wheeler,William R.; Adiletta,Matthew J., Gate estimation process and method.
  18. Wheeler, William R.; Adiletta, Mathew J.; Fennell, Timothy J., Generating a function within a logic design using a dialog box.
  19. Wheeler,William R.; Adiletta,Matthew J., Generating a logic design.
  20. Szpak, Peter; Erkkinen, Thomas J., Graphical model preparation for embedded deployment.
  21. Szpak, Peter; Erkkinen, Thomas J., Graphical model preparation for embedded deployment.
  22. Zhang, Xisheng, Graphical user interface for viewing intermediate calculations from a device model.
  23. Pachner, Daniel, Identification approach for internal combustion engine mean value models.
  24. Wheeler,William R.; Fennell,Timothy J.; Adiletta,Matthew J., Logic simulation.
  25. Paterson,Thomas S.; Bangs,Alex L., Method and apparatus for conducting linked simulation operations utilizing a computer-based system model.
  26. Paterson,Thomas S.; Bangs,Alex L., Method and apparatus for conducting linked simulation operations utilizing a computer-based system model.
  27. Gu, Ke-Qin; Chen, Tsung-Yen (Eric); Han, Ching-Chih (Jason); Lee, Kuo-Chun, Method and apparatus for rendering an IC design layout employing graphics files at low zoom-in factors.
  28. Bryan, Paul David; Hofmann, Richard Gerard; LaFauci, Peter Dean; Lee, William Robert; Mitchell, Rhonda Gurganious; Oke, Timothy Patrick, Method and system for efficiently generating parameterized bus transactions.
  29. Kihas, Dejan, Method and system for updating tuning parameters of a controller.
  30. Kihas, Dejan, Method and system for updating tuning parameters of a controller.
  31. Alley, Charles Lenier; Bybell, Anthony Joseph, Methods for reconstructing data from simulation models.
  32. Wheeler,William R.; Adiletta,Matthew J.; Clark,Christopher; Fennel,Timothy J., Model-based logic design.
  33. Wheeler,William R.; Fennell,Timothy J., Modeling a logic design.
  34. Wolrich,Gilbert; Adiletta,Matthew J.; Gorius,Aaron; Hooper,Donald F.; Carrigan,Douglass; Vora,Chandra, Network device switch.
  35. Stewart, Gregory; Shahed, Syed M.; Borrelli, Francesco; Hampson, Gregory J., Pedal position and/or pedal change rate for use in control of an engine.
  36. Wheeler, William R.; Adiletta, Matthew J., Real-time connection error checking method and process.
  37. Alley, Charles Lenier; Bybell, Anthony Joseph, Reconstruction of data from simulation models.
  38. Alley, Charles Lenier; Bybell, Anthony Joseph, Reconstruction of data from simulation models.
  39. Fennell, Timothy J.; Wheeler, William R., Representing a simulation model using a hardware configuration database.
  40. Wheeler,William R.; Adiletta,Matthew J., Simulating a logic design.
  41. Dettinger, Richard D.; Kolz, Daniel P., Strict validation of inference rule based on abstraction environment.
  42. Sakuragi, Makoto, System and method for circuit simulation.
  43. Balaram, Anil P.; Beggs, Kristin M.; Giffel, Barry A.; Morency, Guy M., Technique for generating an analysis equation.
  44. Pekar, Jaroslav; Stewart, Gregory E., Using model predictive control to optimize variable trajectories and system control.
  45. Markham, Thomas R., Vehicle security module system.
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