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Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0227967 (1999-01-11)
우선권정보 JP0082871 (1995-04-07)
발명자 / 주소
  • Yasuda Mitsuru,JPX
  • Sugiyama Hiroyuki,JPX
  • Ito Noriyuki,JPX
  • Yamashita Ryoichi,JPX
  • Konno Tadashi,JPX
  • Abe Yasunori,JPX
  • Bizen Naomi,JPX
  • Maruyama Terunobu,JPX
  • Kato Yoshiyuki,JPX
  • Isomura T
출원인 / 주소
  • Fujitsu Limited, JPX
대리인 / 주소
    Armstrong, Westerman, Hattori, McLeland & Naughton
인용정보 피인용 횟수 : 66  인용 특허 : 30

초록

A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control

대표청구항

[ What is claimed is:] [1.]1. A circuit designing apparatus of an interactive type having a display unit for displaying circuit design steps and an input unit for inputting responsive information to displayed data on said display unit and information necessary for a circuit design in order to conduc

이 특허에 인용된 특허 (30)

  1. Lewis Lawrence E. (Kirkland WA) Meredith Michael S. (Redmond WA), Automated development of timing diagrams for electrical circuits.
  2. Arakawa Hiroshi (Odawara JPX) Shimada Masao (Hadano JPX) Nakada Isao (Hadano JPX), Automatic generating system of connection configuration diagram among units.
  3. Jordan Dale A. (20075 SW. Pecan Aloha OR 97006) Fitzsimmons Lynne A. (2905 SW. 107th Portland OR 97225) Greenseth William A. (12255 SW. Foothill Dr. Portland OR 97225) Hoffman Gregory L. (14225 SW. W, Block diagram system and method for controlling electronic instruments with simulated graphic display.
  4. Kawakami Yoshiyuki (Neyagawa JPX) Toyonaga Masahiko (Takatsuki JPX), Channel routing method.
  5. Lazansky Richard W. (Pleasanton CA) Miller Thomas R. (Palo Alto CA) Coelho David R. (Fremont CA) Scott Kenneth E. (Fremont CA) Stanculescu Alec G. (San Mateo CA), Computer-aided engineering.
  6. Ho William Wai Yan, Connectivity-based approach for extracting parasitic layout in an integrated circuit.
  7. Kaiser Richard R. (10810 NW. La Cassel Crest La. Portland OR 97229) Bartel Robert W. (Rte. 2 ; P.O. Box 107 Gaston OR 97119), Critical path analyzer with path context window.
  8. Tsay Ren-Song (Palo Alto CA) Chang Chwen-Cher (Fremont CA), Electronic design automation tool for the design of a semiconductor integrated circuit chip.
  9. Wikle Glenn (South Orange NJ) Ramaswamy Suresh (Flanders NJ) Matheson Thomas G. (Brookside NJ), Integrated circuit design apparatus with multiple connection modes.
  10. Sugiyama Yaroku,JPX ; Sugiyama Hiroyuki,JPX ; Ito Noriyuki,JPX ; Yamashita Ryouichi,JPX ; Maruyama Terunobu,JPX ; Abe Yasunori,JPX, Interactive circuit designing apparatus.
  11. Matsumoto Noriko (Kyoto JPX) Takaoka Shoji (Osaka JPX) Ueda Masahiko (Osaka JPX) Nishiyama Tamotsu (Osaka JPX), Logic design system and method in the same.
  12. Pedersen Bruce (San Jose CA), Method and apparatus for assigning and analyzing timing specifications in a computer aided engineering program.
  13. Li Ying-Meng (San Jose CA) Ashtaputre Sunil V. (San Jose CA) Greidinger Jacob (Cupertino CA) Hartoog Mark R. (Los Gatos CA) Hossain Moazzem M. (San Jose CA) Hui Siu-Tong (San Jose CA), Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew.
  14. Dangelo Carlos (Los Gatos CA) Nagasamy Vijay (Union City CA) Ponukumati Vijayanand (Sunnyvale CA), Method and system for creating and validating low level description of electronic design.
  15. Dangelo Carlos (Los Gatos CA) Deeley Richard (San Jose CA) Nagasamy Vijay (Union City CA) Vafai Manoucher (Los Gatos CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
  16. Dangelo Carlos (Los Gatos CA) Watkins Daniel (Los Altos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
  17. Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
  18. Dangelo Carlos ; Nagasamy Vijay ; Ponukumati Vijayanand, Method and system for creating and validating low-level description of electronic design.
  19. Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Watkins Daniel R. (Los Altos CA), Method and system for creating, deriving and validating structural description of electronic system from higher level, b.
  20. Wang Deborah C. (San Jose CA), Method for estimating routability and congestion in a cell placement for integrated circuit chip.
  21. Granato Michael A. (Essex Junction VT) Miceli Gregory F. (Poughkeepsie NY) Relis Jerome R. (Monsey NY) Selinger Craig R. (Spring Valley NY) Watts Vernon L. (Poughkeepsie NY), Method for minimizing the time skew of electrical signals in very large scale integrated circuits.
  22. Dangelo Carlos (San Jose CA) Nagasamy Vijay K. (Mountain View CA) Bootehsaz Ahsan (Santa Clara CA) Rajan Sreeranga P. (Sunnyvale CA), Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and.
  23. Masubuchi Yoshio (Kawasaki JPX), Network path trace apparatus and network path trace method.
  24. Johnson Charles L. (Rochester MN) Lembach Robert F. (Rochester MN) Rudolph Bruce G. (Rochester MN) Williams Robert R. (Rochester MN), Reducing clock skew in large-scale integrated circuits.
  25. Lee Kaiwin (Sunnyvale CA) Chung Lu (Sunnyvale CA) Lin Chin-Hsen (Milpitas CA) Liao Yuh-Zen (Saratoga CA) Wuu Stephen (Sunnyvale CA), Routing algorithm method for standard-cell and gate-array integrated circuit design.
  26. Nishio Seiichi (Kawasaki JPX), Signal tracing apparatus for logic circuit diagrams.
  27. Hyduke Stanley M. (3525 Old Conejo Rd. ; Ste. #111 Newbury Park CA 91320), Simulation of selected logic circuit designs.
  28. Rostoker Michael D. (San Jose CA) Watkins Daniel R. (Los Altos CA), System and method for creating and validating structural description of electronic system.
  29. Watkins Daniel (Los Altos CA) Werner Jeffrey A. (Santa Clara CA) Hweizen H. I. (San Jose CA), System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data.
  30. Satoh Yasuo (Ohme JPX) Itoh Takuji (Ohme JPX), Wiring routes in a plurality of wiring layers.

이 특허를 인용한 특허 (66)

  1. Yamazaki, Naomi, Apparatus for displaying mounting state of device.
  2. Kikuchi, Hideo; Yato, Arata, Automatic parts placement system, method, and medium.
  3. Grinchuk, Mikhail I.; Andreev, Alexander E.; Scepanovic, Ranko, Cell pin extensions for integrated circuits.
  4. Giffel, Barry A., Connection navigation in electronic design automation.
  5. Young, Jay T.; Abid, Salim, Dedicated resource placement enhancement.
  6. Keiichi Kurokawa JP; Masahiko Toyonaga JP; Takuya Yasui JP, Delay analysis method and design assist apparatus of semiconductor circuit.
  7. Kurokawa, Keiichi; Toyonaga, Masahiko; Yasui, Takuya, Delay analysis method and design assist apparatus of semiconductor circuit.
  8. Demizu, Kouji; Kidera, Masayuki, Design support system, method and storage medium for a route design for a deformable linear structure.
  9. Chuang, Yi-Lin; Ku, Chun-Cheng; Lee, Yun-Han; Wang, Shao-Yu; Changchien, Wei-Pin; Liu, Chin-Chou, Group bounding box region-constrained placement for integrated circuit design.
  10. Kohli, Vikas; Durrill, Steven R., Hierarchical editing of printed circuit board pin assignment.
  11. Kozhaya,Joseph N.; Ryan,Patrick M., I/O circuit power routing system and method.
  12. Allen, Robert J; Baker, Faye D; Chu, Albert M; Gray, Michael S; Hibbeler, Jason; Maynard, Daniel N; Tan, Mervyn Y; Walker, Robert F, IC layout optimization to improve yield.
  13. Okano,Motochika; Ikeda,Kazushi; Matsuda,Kazuyuki, Information display system and information display method.
  14. Amano,Yasuo; Seki,Hiroshi; Makino,Yukio; Yamanishi,Yumiko; Nakanishi,Yoshiko; Ishikawa,Yoichiro, Integrated circuit design apparatus, method and program evaluating condition of functional blocks, assigned to virtual placement regions in each of lower-and higher-rank mounting blocks.
  15. Goh, Denis Chuan Hu; Ong, Goet Kwone; Chew, Chai Pin, Interactive configuration of connectivity in schematic diagram of integrated circuit design.
  16. Bosshart, Patrick W., Interactive routing editor with symbolic and geometric views for integrated circuit layout.
  17. Okabe, Hideyuki, Layout design program, layout design device and layout design method for semiconductor integrated circuit.
  18. Fukunaga, Sawako; Takahashi, Yuuki; Yamashita, Katsuhiro, Layout device and layout method of semiconductor integrated circuit.
  19. Tanaka, Toshio, Layout system, layout program, and layout method for text or other layout elements along a grid.
  20. Sugibayashi, Tadahiko, Library for use in designing a semiconductor device.
  21. Hiroyuki Tada JP, Method and apparatus for compacting wiring layout.
  22. Teig,Steven; Deretsky,Zachary, Method and apparatus for computing capacity of a region for non-Manhattan routing.
  23. Teig,Steven; Ganley,Joseph L., Method and apparatus for considering diagonal wiring in placement.
  24. Teig,Steven; Caldwell,Andrew, Method and apparatus for decomposing a region of an integrated circuit layout.
  25. Teig,Steven; Caldwell,Andrew, Method and apparatus for decomposing a region of an integrated circuit layout.
  26. Teig,Steven; Frankle,Jonathan; Jacques,Etienne, Method and apparatus for performing an exponential path search.
  27. Teig,Steven; Ganley,Joseph L., Method and apparatus for placing circuit modules.
  28. Teig,Steven; Frankle,Jonathan, Method and apparatus for routing.
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  30. Teig,Steven; Frankle,Jonathan; Jacques,Etienne; Caldwell,Andrew, Method and apparatus for routing.
  31. Frankle, Jonathan; Caldwell, Andrew, Method and apparatus for routing with independent goals on different layers.
  32. Frankle,Jonathan; Caldwell,Andrew, Method and apparatus for routing with independent goals on different layers.
  33. Teig,Steven; Frankle,Jonathan, Method and apparatus for searching for a global path.
  34. Teig,Steven; Frankle,Jonathan, Method and apparatus for searching for a three-dimensional global path.
  35. Teig,Steven; Ganley,Joseph L., Method and apparatus for using connection graphs with potential diagonal edges to model interconnect topologies during placement.
  36. Roberts, Mark B.; Roberts, Scott K., Method and system for generating implementation files from a high level specification.
  37. Roberts, Mark B.; Roberts, Scott K., Method and system for generating multiple implementation views of an IC design.
  38. Teig,Steven, Method and system for performing placement on non Manhattan semiconductor integrated circuits.
  39. Frankle, Jonathan; Gilchrist, III, John H.; Malhotra, Anish, Method and system for routing.
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  49. Ito, Noriyuki; Yamashita, Ryoichi; Osawa, Keiko; Isomura, Tomoyuki; Hanamitsu, Hiroaki; Katagiri, Hideaki, Placement/net wiring processing system.
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  52. Teig,Steven; Wang,Maogang, Post processor for optimizing manhattan integrated circuits placements into non manhattan placements.
  53. Masafumi Kitahara JP, Route determination support device, route determination support method and storage medium storing therein program for executing method thereof, and printed substrate wiring method.
  54. Kobayashi, Masato, Signal processing device.
  55. Kannan, Parivallal; Stern, Carl M., Skew-driven routing for networks.
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  58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  59. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  60. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  63. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  64. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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