초록 ▼

A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a pla

A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

대표청구항 ▼

[ What is claimed is:] [1.]1. A semiconductor device structure having improved alignment to underlying topography comprising:a semiconductor device or assembly having a reflective, non-planar surface;a planar-surfaced layer formed over the reflective, non-planar surface of the semiconductor device o

[ What is claimed is:] [1.]1. A semiconductor device structure having improved alignment to underlying topography comprising:a semiconductor device or assembly having a reflective, non-planar surface;a planar-surfaced layer formed over the reflective, non-planar surface of the semiconductor device or assembly, the planar-surfaced layer having a first index of refraction;a corrective layer formed over the planar-surfaced layer, the corrective layer having an intermediate index of refraction; anda process layer formed over the corrective layer, the process layer having a second index of refraction, wherein the intermediate index of refraction lies between the first index of refraction and the second index of refraction.