초록 ▼

A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is in communication with a host server and external peripheral devices. Each I/O control logic unit includes

A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is in communication with a host server and external peripheral devices. Each I/O control logic unit includes a processor, a memory, and a memory controller. A master I/O control logic unit services I/O transactions from the host server and the external peripheral devices. A slave I/O control logic unit operates in a quiescent state until the master I/O control logic unit experiences a memory failure. At such time, the slave I/O control logic unit resumes operation of the I/O controller. In order to facilitate the switchover from the master I/O control logic unit to the slave I/O control logic unit, the master memory controller performs concurrent memory write operations in both the master and slave memories. The concurrent memory write operations ensure that the memories in both I/O control logic units are in a consistent state in order for the switchover to occur without loss of data.

대표청구항 ▼

[ What is claimed is:] [1.]1. An apparatus for controlling a data transfer between a data processor and a data unit, comprising:a first control unit having a capability to control the data transfer between the data processor and the data unit, comprising:a first memory controller generating a first

[ What is claimed is:] [1.]1. An apparatus for controlling a data transfer between a data processor and a data unit, comprising:a first control unit having a capability to control the data transfer between the data processor and the data unit, comprising:a first memory controller generating a first address signal, a first control signal, and a first switch control signal;a first memory device coupled to the first memory controller, the first memory device receives the first address signal, the first control signal, and a first data signal to perform a memory access; anda first switch control unit that allows the first control unit to receive data values for the first address signal, the first control signal, and the first data signal, the first switch control unit coupled to the first switch control signal, and the first address signal, the first control signal, and the first data signal;a second control unit that controls the data transfer between the data processor and the data unit, comprising:a second memory controller generating a second address signal, a second control signal, and a second switch control signal;a second memory device coupled to the second memory controller, the second memory device receives the second address signal, the second control signal, and a second data signal, to perform a memory access; anda second signal switch control unit that allows the second control unit to transmit data values from the second address signal to the first address signal, from the second control signal to the first control signal, and from the second data signal to the first data signal, the second signal switch control unit coupled to the second switch control signal, the second address signal, the second control signal, and the second data signal.