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Compiler for optimizing memory instruction sequences by marking instructions not having multiple memory address paths 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0116136 (1998-07-15)
우선권정보 JP0192262 (1997-07-17)
발명자 / 주소
  • Odani Kensuke,JPX
  • Tanaka Akira,JPX
  • Tanaka Hirohisa,JPX
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd., JPX
인용정보 피인용 횟수 : 97  인용 특허 : 14

초록

Internal variables generated by a compiler are assigned to machine resources such as registers and memory by the resource assigning unit 11, and when the assembler code generation unit 18 has outputted an instruction sequence, the alias accessibility analyzing unit 19 registers memory access instruc

대표청구항

[ What is claimed is:] [1.]1. An optimizing apparatus for optimizing a sequence of instructions obtained as a result of a compiler translating a source program composed of statements written in a programming language, wherein the compiler includes resource assigning means for assigning a plurality o

이 특허에 인용된 특허 (14)

  1. Besaw Keith V. (Rochester MN) Donovan Robert J. (Rochester MN) Sagiv Shmuel (Ramat Hasharon ILX), Complier and method for alias checking in a complier.
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  4. Chernoff Anton ; Yates John S., Means and apparatus for maintaining condition codes in an unevaluated state.
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  7. King Stephen E. (Phoenix AZ), Minimizing hardware pipeline breaks using software scheduling techniques during compilation.
  8. Odani Kensuke,JPX ; Sayama Junko,JPX ; Tanaka Akira,JPX, Optimization apparatus for removing hazards by arranging instruction order.
  9. Hsu Wei ; Staley Loren, Optimizing compiler having data cache prefetch spreading.
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  12. Spix George A. (Eau Claire WI) Wengelski Diane M. (Eau Claire WI) Hawkinson Stuart W. (Eau Claire WI) Johnson Mark D. (Eau Claire WI) Burke Jeremiah D. (Eau Claire WI) Thompson Keith J. (Eau Claire W, System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel executi.
  13. Burke Michael G. (Yonkers NY) Choi Jong-Deok (Mount Kisco NY) Cytron Ronald G. (University City MO), System and method for optimizing computer code using a compact data flow representation.
  14. Iwashita Hiroaki (Kawasaki JPX), System for automatic generating instruction string to verify pipeline operations of a processor by inputting specificati.

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  26. Wang, Cheng; Wu, Youfeng, Expediting execution time memory aliasing checking.
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  46. Guo, Xiaofeng; Dai, Jinquan; Li, Long, Method and apparatus for merging critical sections.
  47. Srivastava,Alok K.; Chatterjee,Surojit, Method and mechanism for diagnosing computer applications using traces.
  48. Chung, Shine C., Method and structure for reliable electrical fuse programming.
  49. Chung, Shine C., Method and structure for reliable electrical fuse programming.
  50. Chung, Shine C., Method and system of programmable resistive devices with read capability using a low supply voltage.
  51. Babaian, Boris A.; Okunev, Sergey K.; Volkonsky, Vladimir Y., Method for removing dependent store-load pair from critical path.
  52. Arsenault, David, Modifying browser requests to track browsing activities.
  53. Chung, Shine C., Multiple-bit programmable resistive memory using diode as program selector.
  54. Chung, Shine C., Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory.
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  56. Chung, Shine C., OTP memory with high data security.
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  75. Chung, Shine C., Programmable resistive devices using Finfet structures for selectors.
  76. Chung, Shine C., Programmable resistive memory unit with data and reference cells.
  77. Chung, Shine C., Programmable resistive memory unit with multiple cells to improve yield and reliability.
  78. Chung, Shine C., Programmably reversible resistive device cells using CMOS logic processes.
  79. Chung, Shine C., Programmably reversible resistive device cells using CMOS logic processes.
  80. Chung, Shine C., Programmably reversible resistive device cells using polysilicon diodes.
  81. George, Biju; Lueh, Guei-Yuan, Register liveness analysis for SIMD architectures.
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  83. Chung, Shine C., Reversible resistive memory using diodes formed in CMOS processes as program selectors.
  84. Chung, Shine C., Reversible resistive memory using polysilicon diodes as program selectors.
  85. Wilkerson, Christopher B.; Srinivasan, Srikanth T.; Ju, Dz-ching, Runtime critical load/data ordering.
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  89. Harada, Larry T.; Dolecki, Mark A.; Purdum, Christopher S.; Hendren, III, C. Hudson, Secure data exchange between data processing systems.
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  91. Harada, Larry T.; Dolecki, Mark A.; Purdum, Christopher S; Hendren, III, C. Hudson, Secure data exchange for processing requests.
  92. Chung, Shine C., Sensing circuit for programmable resistive device using diode as program selector.
  93. Chung, Shine C., Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection.
  94. Chung, Shine C., Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC.
  95. Chung, Shine C., Structures and techniques for using semiconductor body to construct bipolar junction transistors.
  96. Chung, Shine C., System and method of a novel redundancy scheme for OTP.
  97. Chung, Shine C., System and method of in-system repairs or configurations for memories.
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