초록 ▼

A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photore

A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method of forming an interconnect structure comprising the steps of:(a) depositing a first insulator layer upon a substrate;(b) depositing an etch stop layer upon said first insulator layer;(c) depositing a second insulator layer on top of said etch stop layer;(d) for

[ What is claimed is:] [1.]1. A method of forming an interconnect structure comprising the steps of:(a) depositing a first insulator layer upon a substrate;(b) depositing an etch stop layer upon said first insulator layer;(c) depositing a second insulator layer on top of said etch stop layer;(d) forming a first mask atop of said second insulator layer;(e) etching said first insulator layer, said etch stop layer and said second insulator layer in a single step to define a via;(f) removing said first mask;(g) forming a second mask to define a trench;(h) etching said second insulator layer as defined by said second mask to form a trench; and(i) metalizing said via and said trench to form an interconnect structure.