초록 ▼

Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. a dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previou

Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. a dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previous metallization layer (e.g., the conductive plug). This scheme effectively eliminates the effect of CMP-induced erosion on the etch-stop layer and therefore allows an extremely thin etch stop to be used. Moreover, a high etch-selectivity can be obtained for the trench etch, and all etch-stop material is removed from beneath the interconnect metal, thereby reducing parasitic effects. A patterned dielectric layer is used as a metal cap in place of the standard blanket silicon nitride layer, thus preventing the formation of blisters and bubbles associated with trapped moisture and gasses, and reducing interconnect capacitance.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method for forming an interconnect to a conductor in an integrated circuit, said method comprising the steps of:(a) forming a first dielectric layer over said conductor;(b) patterning said first dielectric layer to create a first opening extending to said conductor;(c

[ What is claimed is:] [1.]1. A method for forming an interconnect to a conductor in an integrated circuit, said method comprising the steps of:(a) forming a first dielectric layer over said conductor;(b) patterning said first dielectric layer to create a first opening extending to said conductor;(c) forming a conductive plug within said first opening such that said conductive plug substantially fills said first opening and is electrically continuous with said conductor;(d) forming an etch-stop layer on said first dielectric layer and said conductive plug;(e) forming a second dielectric layer on said etch-stop layer;(f) patterning said second dielectric layer and said etch-stop layer to form an interconnect channel such that said dielectric layer and said etch-stop layer exhibit different etch rates;(g) forming an interconnect metal layer over said second dielectric layer and within said interconnect channel such that said interconnect metal layer is electrically continuous with said conductive plug;(h) removing excess regions of said interconnect metal layer from said second dielectric layer to form a substantially planar surface.