초록 ▼

A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the outp

A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the output of the instruction register, and the instruction decoder receives the output of the instruction register. Additionally, a first circuit produces a repetition signal if a received instruction is a repetition instruction, and a second circuit outputs a value from the received instruction to the presetting register when the received instruction is a repetition instruction. A third circuit produces an instruction execution signal that is supplied to the counter, and the first multiplexer is controlled so as to supply the instruction register based on a control output of the counter. The present invention also provides a method of handling instructions to be repeated by a processor.

대표청구항 ▼

[ What is claimed is:] [1.]1. A processor comprising:an instruction extraction stage capable of receiving information from an instruction memory;an instruction register;a first multiplexer receiving at one input an output of the extraction stage and at another input an output of the instruction regi

[ What is claimed is:] [1.]1. A processor comprising:an instruction extraction stage capable of receiving information from an instruction memory;an instruction register;a first multiplexer receiving at one input an output of the extraction stage and at another input an output of the instruction register, an output of the first multiplexer being supplied to the instruction register;an instruction decoder receiving the output of the instruction register;a first circuit in the instruction decoder that determines whether a received instruction is a repetition instruction, the first circuit producing a repetition signal in accordance with its determination;an autonomous counter with a presetting register;a second circuit that, at least when the received instruction is a repetition instruction, outputs a value contained in the received instruction to the presetting register of the counter; anda third circuit producing an instruction execution signal that is supplied to the counter,wherein the first multiplexer is controlled based on a control output of the counter.