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Substrate with die area having same CTE as IC 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/00
출원번호 US-0290776 (1999-04-13)
발명자 / 주소
  • Sylvester Mark F.
출원인 / 주소
  • W. L. Gore & Associates, Inc.
대리인 / 주소
    Genco, Jr.
인용정보 피인용 횟수 : 20  인용 특허 : 23

초록

A package for mounting an integrated circuit chip includes a body having at least a first region, the size of the integrated circuit chip, and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region app

대표청구항

[ What is claimed is:] [1.]1. The combination of a microchip and a substrate, said microchip having a coefficient of thermal expansion, said microchip having an area, said microchip being mounted on said substrate, said combination comprising:a die area defined on the substrate, said die area substa

이 특허에 인용된 특허 (23)

  1. Derryberry Lesli A. (Dallas TX) Williams Charles E. (Dallas TX), A chip carrier and mounting structure connected to the chip carrier.
  2. Sylvester Mark F., Chip package mounting structure for controlling warp of electronic assemblies due to thermal expansion effects.
  3. Cohen Isaac (Dix Hills NY) Svoronos William (Hauppauge NY), Composite printed circuit board and manufacturing method thereof.
  4. Bujard Patrice (Courtepin CHX), Heat-conductive adhesive films, laminates with heat-conductive adhesive layers and the use thereof.
  5. Oscilowski Alex A. (Austin TX) Williams Charles E. (Austin TX) Beene Gary L. (Austin TX) Zogas Peter (Austin TX), High-density package.
  6. Gedney Ronald W. (Vestal NY) Sholtes Tamar A. (Endicott NY), IC chip attachment.
  7. Sylvester Mark F., Integrated circuit chip package assembly.
  8. Kresge John S. (Binghamton NY) Light David N. (Friendsville PA) Wu Tien Y. (Endwell NY), Laminated electronic package including a power/ground assembly.
  9. Mahulikar Deepak (Meriden CT), Metal pin grid array package.
  10. Smith Charles (Ramona CA) Akhtar Masyood (San Diego CA) Chau Michael M. (San Diego CA) Savage David (San Diego CA), Metal-ceramic composite lid.
  11. Miura Osamu,JPX ; Miyazaki Kunio,JPX ; Takahashi Akio,JPX ; Wajima Motoyo,JPX ; Watanabe Ryuji,JPX ; Miwa Takao,JPX ; Satsu Yuichi,JPX ; Amagi Shigeo,JPX, Multi-layer wiring structure.
  12. Newton Charles M. (Palm Bay FL) Palmer Edward G. (Melbourne FL) Sanchez Albert (Palm Bay FL) Myers Christopher A. (Palm Bay FL), Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is pro.
  13. Leibowitz Joseph D. (Culver City CA), Multilayer printed circuit board structure.
  14. Mortimer ; Jr. William P. (New Castle DE), Polytetrafluoroethylene film.
  15. Mohammed Juzer (Naperville IL), Printed wiring board with zones of controlled thermal coefficient of expansion.
  16. Bowman Jeffery B. (Flagstaff AZ) Hubis Daniel E. (Elkton MD) Lewis James D. (Flagstaff AZ) Newman Stephen C. (Flagstaff AZ) Staley Richard A. (Flagstaff AZ), Process for producing a high strength porous polytetrafluoroethylene product having a coarse microstructure.
  17. Gore Robert W. (Newark DE), Process for producing porous products.
  18. Ota Kazuhide (Okazaki JPX) Abe Susumu (Toyota JPX), Process for producing ultra-fine ceramic particles.
  19. Tomaszewski Zbigniew (Heilbronn DEX) Trster Gerhard (Heilbronn DEX), RC line.
  20. Haley Kevin (San Jose CA), Tape BGA package die-up/die down.
  21. Ameen Joseph G. (Bear DE) Mortimer ; Jr. William P. (Conowingo MD) Yokimcus Victor P. (Newark DE), Thermally conductive interface.
  22. Wilson James W. (Vestal NY) Engle Stephen R. (Binghamton NY) Moore Scott P. (Apalachion NY), Thermally enhanced ball grid array package.
  23. Powell Kenneth S., Threaded roof fastener and method for using the same.

이 특허를 인용한 특허 (20)

  1. Cynthia Susan Milkovich ; Mark Vincent Pierson ; Charles Gerard Woychik, CTE compensated chip interposer.
  2. Wang,Yung Hui; Horng,Ching Fu, Circuit carrier and manufacturing process thereof.
  3. Japp,Robert; Markovich,Voya; Palomaki,Cheryl; Papathomas,Kostas; Thomas,David L., Circuitized substrate.
  4. Japp, Robert; Papathomas, Kostas, Circuitized substrate with dielectric layer having dielectric composition not including continuous or semi-continuous fibers.
  5. Lin, Wen-Yi; Lin, Po-Yao, Compliant heat spreader for flip chip packaging having thermally-conductive element with different metal material areas.
  6. Japp,Robert; Papathomas,Kostas, Dielectric composition for forming dielectric layer for use in circuitized substrates.
  7. Katsura Hayashi JP, Electrical device mounting wiring board and method of producing the same.
  8. Bolken, Todd O., Flip chip integrated package mount support.
  9. Japp,Robert; Markovich,Voya; Palomaki,Cheryl; Papathomas,Kostas; Thomas,David L., Information handling system including a circuitized substrate having a dielectric layer without continuous fibers.
  10. Sylvester, Mark F.; Hanson, David A.; Petefish, William G., Interconnect module with reduced power distribution impedance.
  11. Memis,Irving; Papathomas,Kostas I., Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same.
  12. Guzek, John; Wood, Dustin, Metal core integrated circuit package with electrically isolated regions and associated methods.
  13. Wirz, Gustav; Herbst, Wolfgang; Ritzmann, Heinz, Method and device for encapsulating an electronic component in particular a semiconductor chip.
  14. Paruchuri,Mohan R., Method of making a printed circuit board.
  15. Japp,Robert; Markovich,Voya; Palomaki,Cheryl; Papathomas,Kostas; Thomas,David L., Method of making circuitized substrate.
  16. Sakai, Norio; Kato, Isao; Isebo, Kazuhiro, Monolithic ceramic electronic component, method for manufacturing the same, and electronic device.
  17. Gektin, Vadim; Copeland, David W., Multi-lid semiconductor package.
  18. Hada, Sayuri; Sueoka, Kuniaki; Taira, Yoichi, Sheet having high thermal conductivity and flexibility.
  19. Kim, Young-bae, Substrate and electronic device including the substrate.
  20. Bates, David A.; Oot, Stephen J.; Street, Robert J.; Rowden, Brian L., Surface mount ceramic package.
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