초록 ▼

The present invention is a versatile time division multiple access ("TDMA") slot allocation unit. In one embodiment, the versatile TDMA slot allocation unit includes a slot counter configured to provide an address representative of a time slot and a slot descriptor table that contains one or more sl

The present invention is a versatile time division multiple access ("TDMA") slot allocation unit. In one embodiment, the versatile TDMA slot allocation unit includes a slot counter configured to provide an address representative of a time slot and a slot descriptor table that contains one or more slot descriptors each of which describes an action that may be performed within the time slot. The slot descriptor table is configured to receive the address and provide the slot descriptor pointed to by the address. In addition, the TDMA slot allocation unit includes a slot descriptor decoder configured to decode the slot descriptor and provide one or more signals.

대표청구항 ▼

[ What is claimed is:] [1.]1. A time division multiple access (TDMA) slot allocation unit in a system having a host processor, comprising:a slot counter to provide an address representative of a time slot;a slot descriptor table including a first port and a second port, said slot descriptor table to

[ What is claimed is:] [1.]1. A time division multiple access (TDMA) slot allocation unit in a system having a host processor, comprising:a slot counter to provide an address representative of a time slot;a slot descriptor table including a first port and a second port, said slot descriptor table to contain one or more slot descriptors each of which describes an action that may be performed within said time slot, said slot descriptor table to receive said address on an address bus of said first port and to provide said slot descriptor corresponding to said address on a data bus of said first port;a device to receive messages for processing, said device to forward messages to the host processor, and to access the slot descriptor table via the second port for reading and/or writing slot descriptors responsive to receiving a time-critical message; anda slot descriptor decoder coupled to the data bus of the first port of the slot descriptor table, said slot descriptor decoder to decode said slot descriptor and to provide one or more signals.