$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semiconductor device and method for manufacturing same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/320.5
출원번호 US-0106208 (1998-06-29)
우선권정보 JP0174198 (1997-06-30)
발명자 / 주소
  • Inumiya Seiji,JPX
  • Hieda Katsuhiko,JPX
  • Matsuda Tetsuo,JPX
  • Ozawa Yoshio,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보 피인용 횟수 : 71  인용 특허 : 1

초록

A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insula

대표청구항

[ What is claimed is:] [9.]9. A method of manufacturing a semiconductor device comprising the steps of:forming a dummy film and a dummy gate pattern at a gate-forming region on a semiconductor substrate;modifying at least a lower edge portion of said dummy gate pattern;forming an interlayer insulati

이 특허에 인용된 특허 (1)

  1. Misra Veena ; Venkatesan Suresh ; Hobbs Christopher C. ; Smith Brad ; Cope Jeffrey S. ; Wilson Earnest B., Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligne.

이 특허를 인용한 특허 (71)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  4. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  5. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  6. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  15. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  16. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  17. Hsu, Sheng Teng; Zhang, Fengyan; Li, Tingkai, MFOS memory transistor & method of fabricating same.
  18. Henson, Kirklen; Rooyackers, Rita; Vanhaelemeersch, Serge; Badenes, Goncal, MIS transistors with a metal gate and high-k dielectric and method of forming.
  19. Tae Kyun Kim KR; Se Aug Jang KR; In Seok Yeo KR, MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness.
  20. Paul R. Besser ; Qi Xiang ; Matthew S. Buynoski, Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process.
  21. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  22. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  23. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  24. Furukawa, Toshiharu; Hakey, Mark C.; Holmes, Steven J.; Horak, David V.; Rabidoux, Paul A., Method for selective trimming of gate structures and apparatus formed thereby.
  25. Lee, Ming-Hsiu, Method of fabricating a contact.
  26. Shin,Jeong Ho; Ahn,Jong Hyon; Cheong,Kong Soo; Jun,Jin Won, Method of forming a metal gate in a semiconductor device.
  27. Hsu, Sheng Teng; Li, Tingkai; Zhang, Fengyan, Method of making a self-aligned ferroelectric memory transistor.
  28. Yagishita, Atsushi; Matsuo, Kouji; Akasaka, Yasushi; Suguro, Kyoichi; Tsunashima, Yoshitaka, Method of manufacturing semiconductor device using dummy gate wiring layer.
  29. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  30. Shin,Hyunsoo; Kim,Kyusung, Methods for forming a field effect transistor.
  31. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  32. Amarnath, Kuldeep; Hargrove, Michael; Samavedam, Srikanth, Methods of forming replacement gate structures with a recessed channel.
  33. Park, Cheolsoo, Methods of manufacturing transistors using dummy gate patterns.
  34. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  35. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  36. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  37. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  38. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  39. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  40. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  41. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  42. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  43. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  44. Bangsaruntip, Sarunya; Cohen, Guy; Guillorn, Michael A., Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric.
  45. Bangsaruntip, Sarunya; Cohen, Guy; Guillorn, Michael A., Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric.
  46. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  47. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  48. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  49. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  50. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  51. Ozawa,Yoshio; Suizu,Yasumasa; Tsunashima,Yoshitaka, Semiconductor device and method of manufacture thereof.
  52. Ozawa,Yoshio; Suizu,Yasumasa; Tsunashima,Yoshitaka, Semiconductor device and method of manufacture thereof.
  53. Suguro, Kyoichi, Semiconductor device and method of manufacture thereof.
  54. Wakabayashi, Hitoshi; Saito, Yukishige, Semiconductor device and method of manufacturing the same.
  55. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device comprising a pixel unit including an auxiliary capacitor.
  56. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  57. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  58. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  59. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  60. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  61. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  62. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  63. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  64. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  65. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  66. Amitava Chatterjee ; Wei William Lee ; Greg A. Hames ; Qizhi He ; Maureen Hanratty ; Iqbal Ali, Transistor having an improved gate structure and method of construction.
  67. Hsu,Ju Wang; Shieh,Jyu Horng; Chiang,Ju Chien, Transistor with high dielectric constant gate and method for forming the same.
  68. Beyer, Sven; Hoentschel, Jan; Scheiper, Thilo; Griebenow, Uwe, Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials.
  69. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  70. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  71. Lee, Byoung Hun; Dirahoui, Bachir; Leobandung, Effendi; Su, Tai-Chi, Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로