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Planarized silicon fin device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
출원번호 US-0458531 (1999-12-09)
발명자 / 주소
  • Muller K. Paul L.
  • Nowak Edward J.
  • Wong Hon-Sum P.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Ratner & PrestiaSchnurmann
인용정보 피인용 횟수 : 146  인용 특허 : 10

초록

An improved fin device used as the body of a field effect transistor ("FET") and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor ("MOS") FETs in the size range of micrometers to nanometers, while avoiding the

대표청구항

[ What is claimed is:] [1.]1. A planarized fin device, comprising:a substrate;a vertical fin formed on a portion of the substrate, leaving a remaining portion of the substrate exposed;an oxide layer covering the fin and the exposed substrate;a source and drain formed on top of the oxide layer;a poly

이 특허에 인용된 특허 (10)

  1. Brunner Timothy A. (Ridgefield CT) Hsu Louis L. (Fishkill NY) Mandelman Jack A. (Stormville NY) Wang Li-Kong (Montvale NJ), High performance multi-mesa field effect transistor.
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  9. Lo Guo-Qiang (Patrick) ; Lee Shih-Ked, Structures for preventing gate oxide degradation.
  10. Gonzalez Fernando ; Kao David, Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors.

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