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Method of detecting defects in patterned substrates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/302
출원번호 US-0226967 (1999-01-08)
발명자 / 주소
  • Talbot Christopher G.
  • Lo Chiwoei Wayne
출원인 / 주소
  • Schlumberger Technologies, Inc.
대리인 / 주소
    Skjerven Morrill MacPherson LLP
인용정보 피인용 횟수 : 203  인용 특허 : 7

초록

Defects in a patterned substrate are detected by positioning a charged-particle-beam optical column relative to a patterned substrate, the charged-particle imaging system having a field of view (FOV) with a substantially uniform resolution over the FOV; operating the charged-particle-beam optical co

대표청구항

[ What is claimed is:] [1.]1. A method of detecting defects in a patterned substrate, comprising:(1) positioning a charged-particle-beam optical column relative to a patterned substrate, the charged-particle-beam optical column having a field of view (FOV) greater than approximately 100 microns with

이 특허에 인용된 특허 (7)

  1. Toro-Lira Guillermo L. (Sunnyvale CA) Achilles Alan H. (San Jose CA) Frederick Nolan V. (Boulder CO) Monahan Kevin M. (Cupertino CA) Rigg Philip R. (Saratoga CA), Detection system for precision measurements and high resolution inspection of high aspect ratio structures using particl.
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  3. Meisburger Dan (San Jose CA 4) Brodie Alan D. (Palo Alto CA) Chadwick Curt (Los Gatos CA) Desai Anil (San Jose CA) Dohse Hans (Pleasanton CA) Emge Dennis (San Jose CA) Greene John (Los Altos CA) John, Electron beam inspection system and method.
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  5. Pau Louis F. (Grand-Lancy CHX), Method of examining and testing an electric device such as an integrated or printed circuit.
  6. Mizuno Fumio,JPX, Pattern shape inspection apparatus for forming specimen image on display apparatus.
  7. Mizuno Fumio,JPX, Sample analyzing apparatus.

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  76. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells with first DOE including tip-to-side short configured fill cells and second DOE including chamfer short configured fill cells.
  77. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells.
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  79. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells.
  80. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells.
  81. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configured fill cells.
  82. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells.
  83. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells.
  84. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including corner short configured fill cells.
  85. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including merged-via configured fill cells.
  86. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells.
  87. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells.
  88. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  89. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  90. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  91. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  92. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  93. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  94. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  95. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate.
  96. Shanmugasundram,Arulkumar P.; Schwarm,Alexander T., Integrating tool, module, and fab level control.
  97. Reiss,Terry P.; Shanmugasundram,Arulkumar P.; Schwarm,Alexander T., Integration of fault detection with run-to-run control.
  98. Tsao,Chun Cheng; Delenia,Eugene, Integration of photon emission microscope and focused ion beam.
  99. Frank,Jonathan; Cotton,Daniel, Light beam apparatus and method for orthogonal alignment of specimen.
  100. Chowdhury, Vijay; Hahn, James, Method and apparatus for detecting electrical failures on a die through maximizing passive voltage contrast on its surface.
  101. Suga, Takashi; Uesaka, Kouichi; Nakamura, Satoshi; Hayashi, Yoshihiko, Method and apparatus for determining a magnetic field.
  102. Woods,Gary; Kasapi,Steven; Wilsher,Kenneth, Method and apparatus for measuring high-bandwidth electrical signals using modulation in an optical probing system.
  103. Zhang, Zhao-Li; Fang, Wei; Jau, Jack, Method and system for determining a defect during charged particle beam inspection of a sample.
  104. Hess, Carl; Miller, John D.; Xue, Shan; LoPresti, Patrick, Method and system for hybrid reticle inspection.
  105. Kalburge, Amol M.; Yu, Zhen, Method for determining anisotropy of 1-D conductor or semiconductor synthesis.
  106. Portune,Richard A., Method for local wafer thinning and reinforcement.
  107. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage.
  108. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas.
  109. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas.
  110. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas.
  111. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas.
  112. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas.
  113. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areas.
  114. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas.
  115. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage.
  116. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas.
  117. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage.
  118. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas.
  119. Lee,Byoung Ho; Kim,Deok Yong, Method for selecting reference images, method and apparatus for inspecting patterns on wafers, and method for dividing a wafer into application regions.
  120. Van Der Werf,Jan Evert; Mud,Auke Jan, Method of detecting mask defects, a computer program and reference substrate.
  121. Schwarm,Alexander T.; Shanmugasundram,Arulkumar P.; Pan,Rong; Hernandez,Manuel; Mohammad,Amna, Method of feedback control of sub-atmospheric chemical vapor deposition processes.
  122. Lee,Sang Eun; Han,Jae Sung, Method of identifying and analyzing semiconductor chip defects.
  123. Shinada, Hiroyuki; Takafuji, Atsuko; Ninomiya, Takanori; Sasaki, Yuko; Nozoe, Mari; Murakoshi, Hisaya; Ninomiya, Taku; Kasai, Yuji; Makino, Hiroshi; Kaneko, Yutaka; Tanimoto, Kenji, Method of inspecting a circuit pattern and inspecting instrument.
  124. Shinada,Hiroyuki; Takafuji,Atsuko; Ninomiya,Takanori; Sasaki,Yuko; Nozoe,Mari; Murakoshi,Hisaya; Ninomiya,Taku; Kasai,Yuji; Makino,Hiroshi; Kaneko,Yutaka; Tanimoto,Kenji, Method of inspecting a circuit pattern and inspecting instrument.
  125. Shinada,Hiroyuki; Takafuji,Atsuko; Ninomiya,Takanori; Sasaki,Yuko; Nozoe,Mari; Murakoshi,Hisaya; Ninomiya,Taku; Kasai,Yuji; Makino,Hiroshi; Kaneko,Yutaka; Tanimoto,Kenji, Method of inspecting a circuit pattern and inspecting instrument.
  126. Nozoe, Mari; Shinada, Hiroyuki; Watanabe, Kenji; Saiki, Keiichi; Sugimoto, Aritoshi; Morioka, Hiroshi; Tanaka, Maki; Miyai, Hiroshi, Method of inspecting circuit pattern and inspecting instrument.
  127. Nozoe, Mari; Nishiyama, Hidetoshi; Hijikata, Shigeaki; Watanabe, Kenji; Abe, Koji, Method of inspecting pattern and inspecting instrument.
  128. Ramappa,Deepak A., Method to detect and predict metal silicide defects in a microelectronic device during the manufacture of an integrated circuit.
  129. Kokotov,Yuri; Entin,Efim; Seror,Jacques; Fisher,Yossi; Sarel,Shalomo; Shanmugasundram,Arulkumar P.; Schwarm,Alexander T.; Paik,Young Jeen, Method, system and medium for controlling manufacture process having multivariate input parameters.
  130. Al Bayati,Amir; Adibi,Babak; Foad,Majeed; Somekh,Sasson, Method, system and medium for controlling semiconductor wafer processes using critical dimension measurements.
  131. Shanmugasundram,Arulkumar P.; Armer,Helen; Schwarm,Alexander T., Method, system and medium for process control for the matching of tools, chambers and/or other semiconductor-related entities.
  132. Schwarm,Alexander T.; Shanmugasundram,Arulkumar P.; Seror,Jacques; Kokotov,Yuri; Entin,Efim, Method, system, and medium for handling misrepresentative metrology data within an advanced process control system.
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  138. Somekh, Sasson; Grunes, Howard E., Multi-tool control system, method and medium.
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  155. Nakamura, Takayuki; Murakawa, Tsutomu, Pattern inspection apparatus and pattern inspection method.
  156. Adler, David; Marcus, Matthew, Photoelectron emission microscope for wafer and reticle inspection.
  157. Chen, Jung-Chin; Lee, Cheng-Han, Poly gate silicide inspection by back end etching and by enhanced gas etching.
  158. Kienlen, Gabriel, Positioning device for positioning an aperture plate in an ion beam.
  159. Paik,Young J., Process control by distinguishing a white noise component of a process variance.
  160. Paik,Young Jeen, Process control by distinguishing a white noise component of a process variance.
  161. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  162. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  163. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells.
  164. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells.
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