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Determining a communication schedule between processors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0361316 (1999-07-27)
우선권정보 JP0142440 (1996-05-06)
발명자 / 주소
  • Komatsu Hideaki,JPX
  • Ogasawara Takeshi,JPX
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Gonzalez
인용정보 피인용 횟수 : 44  인용 특허 : 9

초록

Processors which each perform inter-processor communication are sorted into a plurality of groups. A communication graph is generated whose nodes correspond to the groups and edges correspond to the communications. Communication graphs are generated for distances between nodes from one through N-1.

대표청구항

[ What is claimed is:] [1.]1. In a data processing system which has a plurality of processor modules, each of which includes a processor, memory, and interprocessor communication means, and wherein said communication means are able to input and output data at the same time, a method for compiling co

이 특허에 인용된 특허 (9)

  1. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Grice Donald G. (Kingston NY) Kogge Peter M. (Endicott NY) Kuchinski Dav, Advanced parallel array processor(APAP).
  2. Getzinger Thomas W. (La Habra CA) Habereder Hans L. (Anaheim CA) Harrison R. Loyd (Fullerton CA) Hopp Donald M. (Fullerton CA) Mitchell David L. (Fullerton CA) Pian Chao-Kuang (Anaheim CA) Propster J, Data flow signal processor method and apparatus.
  3. Cox George W. (Portland OR) Rattner Justin R. (Aloha OR), Hardware scheduler/dispatcher for data processing system.
  4. Hillis W. Daniel (Brookline MA), Method and apparatus for routing message packets.
  5. Hillis W. Daniel (Brookline MA) Kahle Brewster (Somerville MA) Robertson George G. (Marblehead MA) Steele ; Jr. Guy L. (Lexington MA), Method and apparatus for routing message packets and recording the roofing sequence.
  6. Liebrock Lorie M., Multi-processor parallel computer architecture using a parallel machine with topology-based mappings of composite grid a.
  7. Prasanna G.N. Srinivasa, Multiprocessor scheduling and execution.
  8. Hillis W. Daniel (111 Ivy St. Brookline MA 02146), Parallel processor.
  9. Dahl E. Denning (Malden MA), System and method for generating communications arrangements for routing data in a massively parallel processing system.

이 특허를 인용한 특허 (44)

  1. Blocksome, Michael A.; Miller, Douglas R., Administering an epoch initiated for remote memory access.
  2. Blocksome, Michael A.; Miller, Douglas R., Administering an epoch initiated for remote memory access.
  3. Blocksome, Michael A.; Miller, Douglas R., Administering an epoch initiated for remote memory access.
  4. Faraj, Daniel A.; Smith, Brian E., Administering connection identifiers for collective operations in a parallel computer.
  5. Faraj, Daniel A.; Smith, Brian E., Administering connection identifiers for collective operations in a parallel computer.
  6. Faraj, Daniel A.; Smith, Brian E., Administering connection identifiers for collective operations in a parallel computer.
  7. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Assigning a unique identifier to a communicator.
  8. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Compiling software for a hierarchical distributed processing system.
  9. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Controlling access to a resource in a distributed computing system with a distributed access request queue.
  10. May,Philip E.; Lucas,Brian G.; Moat,Kent D., Dataflow graph compression for power reduction in a vector processor.
  11. Isard, Michael A.; Birrell, Andrew D.; Yu, Yuan, Description language for structured graphs.
  12. Almasi, Gheorghe; Archer, Charles J., Dispatching packets on a global combining network of a parallel computer.
  13. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Distributed administration of a lock for an operational group of compute nodes in a hierarchical tree structured network.
  14. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Distributed hardware device simulation.
  15. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Distributed hardware device simulation.
  16. Shakeri, Mojdeh; Mosterman, Pieter J., Distributed model compilation.
  17. Shakeri,Mojdeh; Mosterman,Pieter J., Distributed model compilation.
  18. Wegman, Mark N.; Rajan, Vadakkedathu T.; Roth, Tova; Kimelman, Douglas N.; Hogstedt, Karin, Dominant edge identification for efficient partition and distribution.
  19. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E.; Xue, Hanhong, Establishing a group of endpoints in a parallel computer.
  20. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E.; Xue, Hanghong, Establishing a group of endpoints to support collective operations without specifying unique identifiers for any endpoints.
  21. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Sidelnik, Albert; Smith, Brian E., Generating an executable version of an application using a distributed compiler operating on a plurality of compute nodes.
  22. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Identifying data communications algorithms of all other tasks in a single collective operation in a distributed processing system.
  23. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Identifying data communications algorithms of all other tasks in a single collective operation in a distributed processing system.
  24. Kimelman,Douglas N.; Rajan,Vadakkedathu T.; Roth,Tova; Wegman,Mark N.; Hogstedt,Karin, Independent net task identification for efficient partition and distribution.
  25. Acher, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Locality mapping in a distributed processing system.
  26. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Locality mapping in a distributed processing system.
  27. Norris,James M.; May,Philip E.; Moat,Kent D.; Essick, IV,Raymond B.; Lucas,Brian G., Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values.
  28. May,Philip E.; Essick, IV,Raymond B.; Lucas,Brian G.; Moat,Kent D.; Norris,James M., Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters.
  29. Miller, Douglas R., Minimally buffered data transfers between nodes in a data communications network.
  30. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Pacing network traffic among a plurality of compute nodes connected using a data communications network.
  31. Das, Dibyendu; Kathiresan, Nagarajan; Ravindran, Rajan; Venkatsubramaniam, Bhaskaran, Process mapping in parallel computing.
  32. Das, Dibyendu; Kathiresan, Nagarajan; Ravindran, Rajan; Venkatsubramaniam, Bhaskaran, Process mapping in parallel computing.
  33. Das, Dibyendu; Kathiresan, Nagarajan; Ravindran, Rajan; Venkatsubramaniam, Bhaskaran, Process mapping parallel computing.
  34. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Sidelnik, Albert; Smith, Brian E., Providing policy-based application services to an application running on a computing system.
  35. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Sidelnik, Albert; Smith, Brian E., Providing policy-based operating system services in a hypervisor on a computing system.
  36. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Sidelnik, Albert; Smith, Brian E., Providing policy-based operating system services in an operating system on a computing system.
  37. Faraj, Daniel A.; Smith, Brian E., Runtime optimization of an application executing on a parallel computer.
  38. Faraj, Daniel A.; Smith, Brian E., Runtime optimization of an application executing on a parallel computer.
  39. Faraj, Daniel A.; Smith, Brian E., Runtime optimization of an application executing on a parallel computer.
  40. Isard, Michael A., Runtime optimization of distributed execution graph.
  41. May,Philip E.; Moat,Kent Donald; Essick, IV,Raymond B.; Chiricescu,Silviu; Lucas,Brian Geoffrey; Norris,James M.; Schuette,Michael Allen; Saidi,Ali, Scheduler of program instructions for streaming vector processor having interconnected functional units.
  42. Lucas,Brian Geoffrey; May,Philip E.; Moat,Kent Donald; Essick, IV,Raymond B.; Chiricescu,Silviu; Norris,James M.; Schuette,Michael Allen; Saidi,Ali, Streaming vector processor with reconfigurable interconnection switch.
  43. Archer, Charles J.; Blocksome, Michael A.; Randles, Amanda E.; Ratterman, Joseph D.; Smith, Brian E., Thread selection according to power characteristics during context switching on compute nodes.
  44. Archer, Charles J.; Blocksome, Michael A.; Peters, Amanda E.; Ratterman, Joseph D.; Smith, Brian E., Thread selection according to predefined power characteristics during context switching on compute nodes.
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