초록 ▼

A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the s

A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:forming memory cell selection MISFETs in a memory cell array region on a principal surface of a semiconductor substrate and forming peripheral circuit MISFETs or logic circuit M

[ What is claimed is:] [1.]1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:forming memory cell selection MISFETs in a memory cell array region on a principal surface of a semiconductor substrate and forming peripheral circuit MISFETs or logic circuit MISFETs in a peripheral circuit region or logic circuit region on said semiconductor substrate, respectively;forming a first insulating film which covers said memory cell selection MISFETs and said peripheral circuit MISFETs or logic circuit MISFETs;forming bit lines over said first insulating film in said memory cell array region;forming a second insulating film which covers said bit lines;forming a lower electrode for each of a plurality of information storage capacitive elements, a capacitive insulating film covering each lower electrode, and an upper electrode over each second insulating film in said memory cell array region;forming a third insulating film over each information storage capacitive element; andflattening the surface of said third insulating film by a CMP method, thereafter defining interconnection grooves and connecting holes in the flattened third insulating film and a lower insulating film thereof in said peripheral circuit region or logic circuit region, successively depositing a first conductive layer and a second conductive layer over the third insulating film contained in the interior of said interconnection grooves and connecting holes, removing the first and second conductive layers on the surface of said third insulating film by the CMP method, and forming interconnections comprised of the first and second conductive layers within each interconnection groove and forming connecting portions comprised of the first and second conductive layers within each connected hole.