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Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/30
  • H01L-021/46
  • H01L-021/322
  • H01L-021/20
  • H01L-021/36
출원번호 US-0255231 (1999-02-22)
발명자 / 주소
  • Linn Jack H.
  • Speece William H.
  • Shlepr Michael G.
  • Rouse George V.
출원인 / 주소
  • Intersil Corporation
대리인 / 주소
    Jaeckle Fleischmann & Mugel, LLP
인용정보 피인용 횟수 : 39  인용 특허 : 8

초록

In a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits, a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form

대표청구항

[ What is claimed is:] [1.]1. A method for forming a bonded semiconductor-on-insulator substrate for semiconductor devices and integrated circuits, said method comprising:providing a wafer comprising a monocrystalline semiconductor material;implanting ions of the semiconductor material through a sur

이 특허에 인용된 특허 (8)

  1. Hill Dale E. (Kirkwood MO), Gettering.
  2. Baker James W. (Gilbert AZ), Method for making intrinsic gettering sites in bonded substrates.
  3. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  4. Holland Orin Wayne (Oak Ridge TN) Thomas Darrell Keith (Kingston TN) Zhou Dashun (Sunnyvale CA), Processing method for forming dislocation-free SOI and other materials for semiconductor use.
  5. Hori Shizue,JPX ; Osawa Akihiko,JPX ; Baba Yoshiro,JPX ; Yawata Shigeo,JPX, Semiconductor device.
  6. Srikrishnan Kris V., Smart-cut process for the production of thin semiconductor material films.
  7. Wada Kunihiko (Kawasaki JPX), Substrate having semiconductor-on-insulator structure with gettering sites and production method thereof.
  8. Short John P. (Indian Harbor Beach FL) McLachlan Craig J. (Melbourne FL) Rouse George V. (Indialantic FL) Zibrida James R. (Melbourne FL), Wafer bonding using trapped oxidizing vapor.

이 특허를 인용한 특허 (39)

  1. Linn, Jack H.; Speece, William H.; Shlepr, Michael G.; Rouse, George V., Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone.
  2. Lagahe,Chrystelle; Aspar,Bernard; Beaumont,Aur?lie, Formation of a semiconductor substrate that may be dismantled and obtaining a semiconductor element.
  3. Chan, Simon Siu-Sing, Inert atom implantation method for SOI gettering.
  4. Czagas, Joseph A.; Woodbury, Dustin A.; Beasom, James D., Integrated circuit having a device wafer with a diffused doped backside layer.
  5. Czagas, Joseph A.; Woodbury, Dustin A.; Beasom, James D., Integrated circuit having a device wafer with a diffused doped backside layer.
  6. Czagas,Joseph A.; Woodbury,Dustin A.; Beasom,James D., Integrated circuit having a device wafer with a diffused doped backside layer.
  7. Cheung, Nathan W.; En, William G.; Farrens, Sharon N.; Korolik, Mikhail, Method for fabricating multi-layered substrates.
  8. Maekawa,Shinji; Akimoto,Kengo, Method for fabricating thin film transistor.
  9. Endo, Akihiko; Nishihata, Hideki, Method for manufacturing bonded wafer.
  10. Ohtani, Hisashi; Miyanaga, Akiharu; Teramoto, Satoshi; Yamazaki, Shunpei, Method for manufacturing semiconductor device.
  11. Czagas, Joseph A.; Woodbury, Dustin A.; Beasom, James D., Method of forming an integrated circuit having a device wafer with a diffused doped backside layer.
  12. Jiang,Tongbi; Yin,Zhiping, Method of forming semiconductor constructions.
  13. Yamazaki, Shunpei; Nakamura, Osama; Kajiwara, Masayuki; Koezuka, Junichi; Dairiki, Koji; Mitsuki, Toru; Takayama, Toru; Ohnuma, Hideto; Asami, Taketomi; Ichijo, Mitsuhiro, Method of manufacturing a semiconductor device.
  14. Yamazaki, Shunpei; Nakamura, Osamu; Kajiwara, Masayuki; Koezuka, Junichi; Dairiki, Koji; Mitsuki, Toru; Takayama, Toru; Ohnuma, Hideto; Asami, Taketomi; Ichijo, Mitsuhiro, Method of manufacturing a semiconductor device.
  15. Yamazaki, Shunpei; Ohtani, Hisashi, Method of manufacturing a semiconductor device.
  16. Yamazaki,Shunpei; Nakamura,Osamu; Kajiwara,Masayuki; Koezuka,Junichi; Dairiki,Koji; Mitsuki,Toru; Takayama,Toru; Ohnuma,Hideto; Asami,Taketomi; Ichijo,Mitsuhiro, Method of manufacturing a semiconductor device.
  17. Yamazaki,Shunpei; Nakamura,Osamu; Kajiwara,Masayuki; Koezuka,Junichi; Dairiki,Koji; Mitsuki,Toru; Takayama,Toru; Ohnuma,Hideto; Asami,Taketomi; Ichijo,Mitsuhiro, Method of manufacturing a semiconductor device.
  18. Yamazaki,Shunpei; Ohnuma,Hideto; Dairiki,Koji; Mitsuki,Toru; Takayama,Toru; Akimoto,Kengo, Method of manufacturing a semiconductor device.
  19. Yamazaki,Shunpei; Ohtani,Hisashi, Method of manufacturing a semiconductor device.
  20. Hamada,Takashi; Murakami,Satoshi; Yamazaki,Shunpei; Nakamura,Osamu; Kajiwara,Masayuki; Koezuka,Junichi; Takayama,Toru, Method of manufacturing a semiconductor device comprising doping steps using gate electrodes and resists as masks.
  21. Nakamura, Osamu; Yamazaki, Shunpei; Dairiki, Koji; Kajiwara, Masayuki; Koezuka, Junichi; Murakami, Satoshi, Method of manufacturing semiconductor device.
  22. Nakamura, Osamu; Yamazaki, Shunpei; Dairiki, Koji; Kajiwara, Masayuki; Koezuka, Junichi; Murakami, Satoshi, Method of manufacturing semiconductor device.
  23. Nakamura,Osamu; Yamazaki,Shunpei; Dairiki,Koji; Kajiwara,Masayuki; Koezuka,Junichi; Murakami,Satoshi, Method of manufacturing semiconductor device.
  24. Yamazaki,Shunpei; Mitsuki,Toru, Method of manufacturing semiconductor device.
  25. Yamazaki, Shunpei; Nakamura, Osamu; Kajiwara, Masayuki; Koezuka, Junichi, Method of manufacturing semiconductor device and semiconductor device.
  26. Yamazaki,Shunpei; Nakamura,Osamu; Kajiwara,Masayuki; Koezuka,Junichi, Method of manufacturing semiconductor device that includes selectively adding a noble gas element.
  27. Taylor, Jr., William J.; Orlowski, Marius; Gilmer, David C.; Alluri, Prasad V.; Hobbs, Christopher C.; Rendon, Michael J.; Clejan, Iuval R., Method of recrystallizing an amorphous region of a semiconductor.
  28. Lee,Tien Hsi, Methods for transferring a layer onto a substrate.
  29. Alexander Yuri Usenko, Process for lift-off of a layer from a substrate.
  30. Yamazaki,Shunpei; Ohtani,Hisashi; Mitsuki,Toru; Ohnuma,Hideto; Takano,Tamae; Kasahara,Kenji; Dairiki,Koji, Process for manufacturing a semiconductor device.
  31. Yamazaki,Shunpei; Ohtani,Hisashi; Mitsuki,Toru; Ohnuma,Hideto; Takano,Tamae; Kasahara,Kenji; Dairiki,Koji, Process for manufacturing a semiconductor device.
  32. Yamazaki,Shunpei; Arai,Yasuyuki, Process for producing a photoelectric conversion device that includes using a gettering process.
  33. Ohtsuki, Hiroshi; Katada, Mitsutaka; Noto, Nobuhiko; Takeno, Hiroshi; Yoshida, Kazuhiko, SOI (silicon on insulator) structure semiconductor device and method of manufacturing the same.
  34. Jiang,Tongbi; Yin,Zhiping, Semiconductor constructions.
  35. Nakamura, Osamu; Kajiwara, Masayuki; Yamazaki, Shunpei; Ohnuma, Hideto, Semiconductor device and manufacturing method of the same.
  36. Nakamura,Osamu; Kajiwara,Masayuki; Yamazaki,Shunpei; Ohnuma,Hideto, Semiconductor device and manufacturing method of the same.
  37. Nakamura,Osamu; Kajiwara,Masayuki; Koezuka,Junichi; Yamazaki,Shunpei; Kuwabara,Hideaki, Semiconductor device and method for manufacturing the same.
  38. Hamada, Takashi; Murakami, Satoshi; Yamazaki, Shunpei; Nakamura, Osamu; Kajiwara, Masayuki; Koezuka, Junichi; Takayama, Toru, Semiconductor device and method of manufacturing the same.
  39. Hamada,Takashi; Murakami,Satoshi; Yamazaki,Shunpei; Nakamura,Osamu; Kajiwara,Masayuki; Koezuka,Junichi; Takayama,Toru, Semiconductor device and method of manufacturing the same.
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